IDT72V271LA15PF IDT, Integrated Device Technology Inc, IDT72V271LA15PF Datasheet - Page 23

• Manufacturer Part Number: IDT72V271LA15PF
• Description: IC FIFO SS 16384X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V271LA15PF

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72V271LA15PF

NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
3. t
4. PAF is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
2. For FWFT mode: D = maximum FIFO depth. D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
WCLK
RCLK
WCLK
WCLK
NOTES:
1. n = PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
RCLK
RCLK
WEN
WEN
WEN
REN
PAF
REN
In IDT Standard mode: D = 16,384 for the IDT72V261LA and 32,768 for the IDT72V271LA.
In FWFT mode: D = 16,385 for the IDT72V261LA and 32,769 for the IDT72V271LA.
the rising edge of RCLK and the rising edge of WCLK is less than t
REN
SKEW2
PAE
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
HF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
t
ENS
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
D - (m+1) words in FIFO
t
CLKL
t
ENH
[
(2)
t
D-1
SKEW2
1
2
,
(3)
t
D/2 words in FIFO
ENH
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
+ 1
(4)
]
words in FIFO
t
t
PAE
CLKH
1
(2)
(1)
2
,
(2)
SKEW2
SKEW2
t
ENS
, then the PAF deassertion time may be delayed one extra WCLK cycle.
t
, then the PAE deassertion may be delayed one extra RCLK cycle.
CLKL
2
23
t
PAF
t
t
ENH
ENS
t
HF
t
ENS
t
SKEW2
n+1 words in FIFO
n+2 words in FIFO
t
ENS
(3)
[
D-1
D/2 + 1 words in FIFO
t
2
ENH
+ 2
t
ENH
D - m words in FIFO
]
(2)
(3)
words in FIFO
,
1
t
HF
1
COMMERCIAL AND INDUSTRIAL
(1)
,
(2)
(2)
TEMPERATURE RANGES
t
PAE
[
D-1
2
2
PAF
PAE
D/2 words in FIFO
2
). If the time between
). If the time between
+ 1
t
PAF
JANUARY 30, 2009
]
words in FIFO
n words in FIFO
n+1 words in FIFO
D-(m+1) words
in FIFO
4673 drw 21
4673 drw 19
4673 drw 20
(1)
,
(2)
(2)
(2)
,
(3)