ADP3208C ON Semiconductor, ADP3208C Datasheet - Page 35

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ADP3208C

Manufacturer Part Number
ADP3208C
Description
7-bit,programmable,dual- Phase,mobile,cpu,synchronous Buck Controller
Manufacturer
ON Semiconductor
Datasheet

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where:
n
R
C
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
where R
Typically, a user wants the highest speed (low C
for a main MOSFET, but such a device usually has higher on
resistance. Therefore, the user must select a device that meets
the total power dissipation (about 0.8 W to 1.0 W for an 8-lead
SOIC) when combining the switching and conduction losses.
For example, an IRF7821 device can be selected as the main
MOSFET (four in total; that is, n
C
T
synchronous MOSFET (four in total; that is, n
R
power dissipation per MOSFET at I
yields 630 mW for each synchronous MOSFET and 590 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
Finally, consider the power dissipation in the driver for each
phase. This is best described in terms of the Q
MOSFETs and is given by the following equation:
where Q
Q
The previous equation also shows the standby dissipation
(I
Ramp Resistor Selection
The ramp resistor (R
ramp. The value of this resistor is chosen to provide the best
combination of thermal balance, stability, and transient response.
Use the following expression to determine a starting value:
P
MF
G
J
ISS
ISS
DS(SF)
DRV
GSF
CC
= 120°C), and an IR7832 device can be selected as the
is the total gate resistance.
is the total number of main MOSFETs.
is the input capacitance of the main MOSFET.
= 1010 pF (maximum) and R
times the VCC) of the driver.
is the total gate charge for each synchronous MOSFET.
P
P
=
= 6.7 mΩ (maximum at T
S
C
(
(
MF
DS(MF)
MF
GMF
2
f
)
)
SW
×
= 2
=
is the total gate charge for each main MOSFET, and
n
is the on resistance of the MOSFET.
×
D
×
(
×
n
f
MF
SW
R
n
) is used to set the size of the internal PWM
×
I
×
MF
O
Q
V
GMF
DC
n
2
MF
+
×
+
12
I
1
n
O
SF
J
×
MF
×
= 120°C). Solving for the
DS(MF)
×
⎛ ×
R
= 4), with approximately
n
Q
O
G
n
= 40 A and I
GSF
MF
×
I
= 18 mΩ (maximum at
n
R
)
n
MF
+
2
I
CC
×
×
SF
G
C
R
ISS
for the
ISS
= 4), with
×
DS
) device
R
VCC
(
MF
= 9.0 A
Rev. 1 | Page 35 of 41 | www.onsemi.com
)
(14)
(15)
(16)
where:
A
A
R
C
Another consideration in the selection of R
internal ramp voltage (see Equation 18). For stability and noise
immunity, keep the ramp size larger than 0.5 V. Taking this into
consideration, the value of R
The internal ramp voltage magnitude can be calculated as follows:
The size of the internal ramp can be increased or decreased. If it
is increased, stability and transient response improves but
thermal balance degrades. Conversely, if the ramp size is
decreased, thermal balance improves but stability and transient
response degrade. In the denominator of Equation 17, the factor
of 3 sets the minimum ramp size that produces an optimal
combination of good stability, transient response, and thermal
balance.
COMP Pin Ramp
In addition to the internal ramp, there is a ramp signal on the
COMP pin due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the
following overall ramp signal at the PWM input:
where C
resistance of the regulator.
For this example, the overall ramp signal is 1.85 V.
DS
R
R
D
is the internal ramp amplifier gain.
is the internal ramp capacitor value.
is the current balancing amplifier gain.
is the total low-side MOSFET ON-resistance,
V
V
V
R
R
R
R
RT
R
R
X
=
=
=
=
=
is the total bulk capacitance, and R
0
A
3
3
462
5 .
1
R
×
×
R
×
5
×
R
A
0
n
k
1 (
×
D
×
1 (
5 .
A
Ω
×
2
5
×
C
R
×
f
×
2 .
×
R
SW
R
×
D
. 0
360
V
(
5
1
×
DS
m
L
)
061
R
×
pF
×
Ω
f
n
C
×
nH
SW
V
R
×
X
×
C
×
)
VID
in this example is selected as 280 kΩ.
D
×
×
5
R
280
)
R
. 1
pF
O
150
kHz
=
462
V
=
k
ADP3208C
. 0
R
Ω
O
is the size of the
83
is the droop
V
(17)
(18)
(19)

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