IDT72V265LA10PFG IDT, Integrated Device Technology Inc, IDT72V265LA10PFG Datasheet - Page 23
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IDT72V265LA10PFG
Manufacturer Part Number
IDT72V265LA10PFG
Description
IC FIFO SS 16384X18 10NS 64-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V255LA10TFG.pdf
(27 pages)
Specifications of IDT72V265LA10PFG
Function
Synchronous
Memory Size
288K (16K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
288Kb
Access Time (max)
6.5ns
Word Size
18b
Organization
16Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
72V265LA10PFG
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V265LA10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V265LA10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 8,192 for the IDT72V255LA and 16,384 for the IDT72V265LA.
2. For FWFT mode: D = maximum FIFO depth. D = 8,193 for the IDT72V255LA and 16,385 for the IDT72V265LA.
IDT72V255LA/72V265LA 3.3 VOLT CMOS SuperSync FIFO™
WCLK
WCLK
RCLK
8,192 x 18, 16,384 x 18
RCLK
WEN
WEN
the rising edge of WCLK and the rising edge of RCLK is less than t
REN
REN
SKEW2
PAE
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
[
ENH
D-1
(2)
t
SKEW2
2
1
,
D/2 words in FIFO
(3)
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
+ 1
(4)
]
words in FIFO
t
t
PAE
CLKH
(1)
,
2
(2)
SKEW2
t
ENS
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
CLKL
23
t
ENH
t
t
ENS
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D-1
D/2 + 1 words in FIFO
2
t
ENH
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
t
PAE
TEMPERATURE RANGES
[
D-1
2
PAE
D/2 words in FIFO
2
+ 1
). If the time between
OCTOBER 22, 2008
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4672 drw 21
4672 drw 20
(1)
,
(2)
(2)
,
(3)