IDT72615L25PF IDT, Integrated Device Technology Inc, IDT72615L25PF Datasheet - Page 3

• Manufacturer Part Number: IDT72615L25PF
• Description: IC FIFO BY SYNC 512X18X2 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72615L25PF

• Function: Synchronous
• Memory Size: 18.4K (512 x 18 x 2)
• Data Rate: 40MHz
• Access Time: 25ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 18Kb
• Access Time (max): 15ns
• Word Size: 18b
• Organization: 512x18x2
• Sync/async: Synchronous
• Expandable: No
• Bus Direction: Bi-Directional
• Package Type: TQFP
• Clock Freq (max): 40MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 230mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72615L25PF

PIN DESCRIPTION
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
D
CS
R/W
EN
OE
A
D
R/W
CLK
EN
OE
EF
PAE
PAF
FF
EF
PAE
PAF
FF
BYP
RS
V
GND
CLK
Symbol
0
CC
A0
B0
, A
AB
BA
AB
BA
A
A
B
A
B
-D
-D
A
B
A
B
AB
BA
AB
BA
B
1
A17
B17
, A
2
Data A
Chip Select A
Read/Write A
Clock A
Enable A
Output Enable A
Addresses
Data B
Read/Write B
Clock B
Enable B
Output Enable B
A→B Empty
Flag
A→B
Programmable
Almost-Empty
Flag
A→B
Programmable
Almost-Full
Flag
A→B Full Flag
B→A Empty
Flag
B→A
Programmable
Almost-Empty
Flag
B→A
Programmable
Almost-Full
Flag
B→A Full Flag
Port B Bypass
Flag
Reset
Power
Ground
Name
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
There are three +5V power pins for the PLCC and two for the TQFP.
Data inputs & outputs for the 18-bit Port A bus.
Port A is accessed when CS
This pin controls the read or write direction of Port A. If R/W
Data A output data is read from Port A. In bypass mode, when R/W
R/W
CLK
When EN
When R/W
in a high-impedance state. If OE
When CS
Data inputs & outputs for the 18-bit Port B bus.
This pin controls the read or write direction of Port B. If R/W
Data B output data is read from Port B. In bypass mode, when R/W
R/W
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLK
When EN
When R/W
in a high-impedance state. If OE
When EF
not empty. EF
through. After the data D
When PAE
programmed into PAE
default offset value for PAE
When PAF
programmed into PAF
offset in PAF
When FF
full. FF
FF
written into Port A.
When EF
passing through. After the data D
When PAE
programmed into PAE
default offset value for PAE
When PAF
programmed into PAF
offset in PAF
When FF
not full. FF
FF
written into Port B.
This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYP
bypass mode. If BYP
A LOW on this pin will perform a reset of all synchronous BiFIFO functions.
There are seven ground pins for the PLCC and four for the TQFP.
is not empty. EF
AB
BA
A
B
A
is LOW, a bypass message is in the register. If FF
is LOW, a bypass message is in the register. If FF
is typically a free running clock. Data is read or written into Port A on the rising edge of CLK
is HIGH, message is read from B→A output register.
is HIGH, message is read from A→B output register.
AB
AB
BA
A
B
AB
BA
A
is synchronized to CLK
AB
BA
A
B
AB
BA
is LOW, data can be read or written to Port A. When EN
is asserted, A
is LOW, data can be read or written to Port B. When EN
BA
is LOW, the A→B FIFO is full and further data writes into Port A are inhibited. When FF
is LOW, the B→A FIFO is full and further data writes into Port B are inhibited. When FF
is LOW, the A→B FIFO is empty and further data reads from Port B are inhibited. When EF
is LOW, the B→A FIFO is empty and further data reads from Port A are inhibited. When EF
is HIGH, Port A is an output bus and OE
is HIGH, Port B is an output bus and OE
AB
BA
is LOW, the A→B FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
is LOW, the B→A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
AB
is LOW, the A→B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
is LOW, the B→A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
is synchronized to CLK
Register. The default offset value for PAF
Register. The default offset value for PAF
BA
is synchronized to CLK
is synchronized to CLK
B
AB
BA
AB
BA
is HIGH, the synchronous BiFIFO passes data into memory. BYP
B0
0
Register. When PAF
Register. When PAF
Register. When PAE
Register. When PAE
, A
-D
AB
BA
1
B17
A
, A
Register is 8. PAE
Register is 8. PAE
is LOW. Port A is inactive if CS
2
B
has been read, EF
A
A0
A
and R/W
is LOW while R/W
is LOW while CS
. In bypass mode, FF
-D
A17
B
. In bypass mode, FF
B
has been read, EF
. In the bypass mode, EF
A
A
3
are used to select one of six internal resources.
. In the bypass mode, EF
AB
AB
BA
BA
AB
BA
is HIGH, the A→B FIFO contains less than or equal to the depth minus the
is HIGH, the A→B FIFO contains more than offset in PAE
is HIGH, the B→A FIFO contains more than offset in PAE
is HIGH, the B→A FIFO contains less than or equal to the depth minus the
AB
A
is synchronized to CLK
is synchronized to CLK
B
A
is LOW and R/W
B
goes LOW.
is HIGH, Port B is in an active (low-impedance) state.
controls the high-impedance state of D
controls the high-impedance state of D
BA
Description
AB
AB
AB
BA
is HIGH, Port A has read the message and another message can be
A
B
BA
BA
tells Port A that a message is waiting in Port B’s output register. If
Register is 8. PAF
is HIGH, Port B has read the message and another message can be
Register is 8. PAF
is LOW, Data A input data is written into Port A. If R/W
is LOW, Data B input data is written into Port B. If R/W
goes LOW on the following cycle.
tells Port B that a message is waiting in Port A’s output register. If
A
is HIGH.
AB
A
B
A
B
is LOW, message is written into A→B output register. If
is LOW, message is written into B→A output register. If
is HIGH, no data transfers occur.
HIGH indicates that data D
BA
is HIGH, no data transfers occur.
A
is HIGH, Port A is in an active (low-impedance) state.
HIGH indicates that data D
B
A
.
.
AB
BA
is synchronized to CLK
is synchronized to CLK
INDUSTRIAL TEMPERATURE RANGE
B
is LOW, Port A has placed the FIFO into
B
is synchronized to CLK
A0
B0
-D
-D
A0
A
.
-D
A17
B17
B
B0
AB
BA
.
A17
-D
. If OE
. If OE
is HIGH, the FIFO is
is HIGH, the FIFO is not
B17
BA
AB
A
B
is available for passing
.
.
AB
BA
is HIGH, the FIFO
is HIGH, the FIFO is
is available for
A
B
Register. The
Register. The
is HIGH, Port A is
is HIGH, Port B is
B
A
B
is HIGH,
.
is HIGH,