IDT72V281L10PF IDT, Integrated Device Technology Inc, IDT72V281L10PF Datasheet - Page 21

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IDT72V281L10PF

Manufacturer Part Number
IDT72V281L10PF
Description
IC FIFO 32768X18 10NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet

Specifications of IDT72V281L10PF

Function
Synchronous
Memory Size
589K (32K x 18)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
576Kb
Access Time (max)
6.5ns
Word Size
9b
Organization
64Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
100MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V281L10PF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT72V281L10PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V281L10PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V281L10PFG
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V281L10PFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. X = 15 for the IDT72V281 and X = 16 for the IDT72V291.
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup procedure.
3. OE = LOW
4. W
5. OR goes LOW at 60ns + 2 RCLK cycles + t
Q
WCLK
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
WCLK
RCLK
0
D = 65,537 for the IDT72V281 and 131,073 for the IDT72V291.
SEN
WEN
REN
- Q
PAE
PAF
LD
1
OR
SI
, W
RT
HF
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
LDS
t
ENS
DS
t
ENS
t
RTS
t
RTS
REF
.
t
t
ENH
LDH
EMPTY OFFSET
t
t
REF
t
ENH
HF
t
SKEW2
1
Figure 12. Retransmit Timing (FWFT Mode)
TM
2
t
PAF
1
W
x+1
BIT X
21
(1)
BIT 0
2
t
PAE
FULL OFFSET
3
t
A
COMMERCIAL AND INDUSTRIAL
t
t
ENH
REF
(5)
W
1
TEMPERATURE RANGES
(4)
t
t
BIT X
LDH
ENH
t
DH
(1)
W
4
2
t
A
4513 drw 16
t
ENH
4513 drw 15
W
3

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