IDT72V281L15PFI IDT, Integrated Device Technology Inc, IDT72V281L15PFI Datasheet - Page 9

• Manufacturer Part Number: IDT72V281L15PFI
• Description: IC FIFO 32768X18 15NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V281L15PFI

• Function: Synchronous
• Memory Size: 589K (32K x 18)
• Data Rate: 67MHz
• Access Time: 15ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V281L15PFI

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
LD
0
0
0
X
1
1
1
8
8
8
8
WEN
X
0
1
1
1
0
1
7
7
7
7
REN
X
1
0
1
1
0
1
72V281 (65,536 x 9›BIT)
EMPTY OFFSET (LSB) REGISTER
FULL OFFSET (MSB) REGISTER
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
EMPTY OFFSET (MSB) REGISTER
SEN
FULL OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
1
1
X
X
X
1
0
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
DEFAULT VALUE
Figure 4. Programmable Flag Offset Programming Sequence
WCLK
Figure 3. Offset Register Location and Default Values
X
X
X
X
TM
RCLK
X
X
X
X
X
Empty Offset (MSB)
Serial shift into registers:
32 bits for the 72V281
Parallel write to registers:
Empty Offset (LSB)
Full Offset (LSB)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Write Memory
Read Memory
No Operation
Ending with Full Offset (MSB)
No Operation
0
0
0
0
9
72V281
8
8
8
8
8
8
7
7
7
7
72V291 (131,072 x 9›BIT)
FULL OFFSET (MID-BYTE) REGISTER
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
EMPTY OFFSET (MID-BYTE) REGISTER
EMPTY OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
FULL OFFSET (LSB) REGISTER
FFH if LD is HIGH at Master Reset
7FH if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
00H if LD is LOW at Master Reset
DEFAULT VALUE
Parallel write to registers:
DEFAULT VALUE
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Serial shift into registers:
34 bits for the 72V291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Write Memory
Read Memory
No Operation
No Operation
DEFAULT VALUE
DEFAULT VALUE
72V291
COMMERCIAL AND INDUSTRIAL
1
1
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
DEFAULT
DEFAULT
FULL OFFSET
4513 drw 06
0H
TEMPERATURE RANGES
0H
0
0
4513 drw 07
0
0
0
0