XC2S50 Xilinx, Inc., XC2S50 Datasheet - Page 65

• Manufacturer Part Number: XC2S50
• Description: Spartan-II 2.5V FPGA Family
• Manufacturer: Xilinx, Inc.

Spartan-II 2.5V FPGA Family: DC and Switching Characteristics
DLL Timing Parameters
Switching parameters testing is modeled after testing meth-
ods specified by MIL-M-38510/605; all devices are 100 per-
cent functionally tested. Because of the difficulty in directly
measuring many internal timing parameters, those parame-
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications were deter-
mined through statistical measurement at the package pins
using a clock mirror configuration and matched drivers.
Module 3 of 4
12
Notes:
1.
2.
3.
4.
5.
Symbol
T
T
T
T
T
T
T
T
PHOOM
OJITCC
PHIOM
IJITCC
IPTOL
PHOO
LOCK
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding output jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
Maximum Phase Difference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges due to DLL alone (excluding input clock jitter).
PHIO
T
T
F
F
Symbol
DLLPWHF
DLLPWLF
CLKINHF
CLKINLF
Input clock period tolerance
Input clock jitter tolerance (cycle-to-cycle)
Time required for DLL to acquire lock
Output jitter (cycle-to-cycle) for any DLL clock output
Phase offset between CLKIN and CLKO
Phase offset between clock outputs on the DLL
Maximum phase difference between CLKIN and CLKO
Maximum phase difference between clock outputs on the DLL
Input clock frequency (CLKDLLHF)
Input clock frequency (CLKDLL)
Input clock pulse width (CLKDLLHF)
Input clock pulse width (CLKDLL)
Description
Description
www.xilinx.com
1-800-255-7778
(2)
(3)
ters are derived from benchmark timing patterns. The fol-
lowing guidelines reflect worst-case values across the
recommended operating conditions.
Figure 1, page
ters in the table below.
50-60 MHz
40-50 MHz
30-40 MHz
25-30 MHz
Min
> 60 MHz
2.0
2.5
60
25
(1)
F
(4)
CLKIN
-6
(5)
Max
200
100
13, provides definitions for various parame-
Speed Grade
-
-
CLKDLLHF
Min
-
-
-
-
-
-
-
-
-
-
-
-
±150
±100
±140
±160
±200
Max
±60
Min
2.4
3.0
1.0
60
25
20
DS001-3 (v2.7) September 3, 2003
-
-
-
-
-5
Min
CLKDLL
-
-
-
-
-
-
-
-
-
-
-
-
Product Specification
Max
180
90
-
-
±300
±100
±140
±160
±200
Max
±60
120
1.0
20
25
50
90
Units
MHz
MHz
Units
ns
ns
ns
ps
µs
µs
µs
µs
µs
ps
ps
ps
ps
ps
R