LM3S1637 Luminary Micro, Inc, LM3S1637 Datasheet - Page 37

• Manufacturer Part Number: LM3S1637
• Description: Lm3s1637 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

1.4.5.3
1.4.6
1.4.6.1
1.4.6.2
1.4.7
1.4.7.1
1.4.7.2
July 25, 2008
When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or
periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
Watchdog Timer (see page 244)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
Memory Peripherals
The LM3S1637 controller offers both single-cycle SRAM and single-cycle Flash memory.
SRAM (see page 142)
The LM3S1637 static random access memory (SRAM) controller supports 32 KB SRAM. The internal
SRAM of the Stellaris
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Flash (see page 143)
The LM3S1637 Flash controller supports 128 KB of flash memory. The flash is organized as a set
of 1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the
block to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
Additional Features
Memory Map (see page 45)
A memory map lists the location of instructions and data in memory. The memory map for the
LM3S1637 controller can be found in “Memory Map” on page 45. Register addresses are given as
a hexadecimal increment, relative to the module's base address as shown in the memory map.
The ARM® Cortex™-M3 Technical Reference Manual provides further information on the memory
map.
JTAG TAP Controller (see page 50)
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and
Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface
for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR)
®
Watchdog Timer module consists of a 32-bit down counter, a programmable load
®
devices is located at offset 0x0000.0000 of the device memory map. To
Preliminary
LM3S1637 Microcontroller
37