LM3S1918 Luminary Micro, Inc, LM3S1918 Datasheet - Page 20
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LM3S1918
Manufacturer Part Number
LM3S1918
Description
Lm3s1918 Arm Microcontroller
Manufacturer
Luminary Micro, Inc
Datasheet
1.LM3S1918.pdf
(489 pages)
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About This Document
About This Document
Audience
About This Manual
Related Documents
Documentation Conventions
20
This data sheet provides reference information for the LM3S1918 microcontroller, describing the
functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3
core.
This manual is intended for system software developers, hardware designers, and application
developers.
This document is organized into sections that correspond to each major feature.
The following documents are referenced by the data sheet, and available on the documentation CD
or from the Luminary Micro web site at www.luminarymicro.com:
■
■
■
■
■
The following related documents are also referenced:
■
This documentation list was current as of publication date. Please check the Luminary Micro web
site for additional documentation, including application notes and white papers.
This document uses the conventions shown in Table 2 on page 20.
Table 2. Documentation Conventions
Notation
General Register Notation
REGISTER
bit
bit field
offset 0xnnn
ARM® Cortex™-M3 Technical Reference Manual
ARM® CoreSight Technical Reference Manual
ARM® v7-M Architecture Application Level Reference Manual
Stellaris
Stellaris
IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture
®
®
Peripheral Driver Library User's Guide
ROM User’s Guide
Meaning
APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and
Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more
than one register. For example, SRCRn represents any (or all) of the three Software Reset Control
registers: SRCR0, SRCR1 , and SRCR2.
A single bit in a register.
Two or more consecutive and related bits.
A hexadecimal increment to a register's address, relative to that module's base address as specified
in “Memory Map” on page 42.
Preliminary
July 26, 2008
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