LM3S6610 Luminary Micro, Inc, LM3S6610 Datasheet - Page 410

• Manufacturer Part Number: LM3S6610
• Description: Lm3s6610 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Reset
Type
Ethernet Controller
Ethernet PHY Management Register 1 – Status (MR1)
Base 0x4004.8000
Address 0x01
Type RO, reset 0x7849
410
Bit/Field
reserved
10:7
15
14
13
12
11
6
5
4
RO
15
0
100X_F
Register 17: Ethernet PHY Management Register 1 – Status (MR1), address
0x01
This register enables software to determine the capabilities of the PHY and perform its initialization
and operation appropriately.
RO
14
1
100X_H
reserved
reserved
RFAULT
RO
100X_H
100X_F
ANEGC
13
10T_H
1
10T_F
Name
MFPS
10T_F
RO
12
1
10T_H
RO
11
1
Type
RO
RO
RO
RO
RO
RO
RO
RO
RC
RO
10
0
Reset
RO
9
0
0
1
1
1
1
0
1
0
0
reserved
Preliminary
RO
8
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
100BASE-TX Full-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Full-Duplex mode.
100BASE-TX Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 100BASE-TX
Half-Duplex mode.
10BASE-T Full-Duplex Mode
When set, indicates that the PHY is capable of 10BASE-T Full-Duplex
mode.
10BASE-T Half-Duplex Mode
When set, indicates that the PHY is capable of supporting 10BASE-T
Half-Duplex mode.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Management Frames with Preamble Suppressed
When set, indicates that the Management Interface is capable of
receiving management frames with the preamble suppressed.
Auto-Negotiation Complete
When set, indicates that the Auto-Negotiation process has been
completed and that the extended registers defined by the
Auto-Negotiation protocol are valid.
Remote Fault
When set, indicates that a remote fault condition has been detected.
This bit remains set until it is read, even if the condition no longer exists.
RO
7
0
MFPS
RO
6
1
ANEGC
RO
5
0
RFAULT
RC
4
0
ANEGA
RO
3
1
LINK
RO
2
0
July 25, 2008
JAB
RC
1
0
EXTD
RO
0
1