LM3S8971 Luminary Micro, Inc, LM3S8971 Datasheet - Page 536

• Manufacturer Part Number: LM3S8971
• Description: Lm3s8971 Arm Microcontroller
• Manufacturer: Luminary Micro, Inc

Signal Tables
536
Pin Name
ERBIAS
GNDPHY
GNDPHY
GNDPHY
CMOD1
Fault
GNDA
GNDA
IDX0
LED0
LED1
MDIO
OSC0
OSC1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HIB
LDO
PA0
PA1
Pin Number
76
41
71
15
21
33
39
45
54
57
63
69
82
87
94
97
42
85
86
51
70
59
60
58
48
49
26
27
9
4
7
Preliminary
Pin Type
I/O
I/O
I/O
I/O
O
O
O
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
I
I
I
I
I
I
Buffer Type
Analog
Analog
Analog
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
Power
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Description
CPU Mode bit 1. Input must be set to logic 0
(grounded); other encodings reserved.
12.4 KOhm resistor (1% precision) used
internally for Ethernet PHY.
PWM Fault
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
Ground reference for logic and I/O pins.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
The ground reference for the analog circuits
(ADC, Analog Comparators, etc.). These are
separated from GND to minimize the electrical
noise contained on VDD from affecting the
analog functions.
GND of the Ethernet PHY
GND of the Ethernet PHY
GND of the Ethernet PHY
An output that indicates the processor is in
hibernate mode.
QEI module 0 index
Low drop-out regulator output voltage. This
pin requires an external capacitor between
the pin and GND of 1 µF or greater. The LDO
pin must also be connected to the VDD25 pins
at the board level in addition to the decoupling
capacitor(s).
MII LED 0
MII LED 1
MDIO of the Ethernet PHY
Main oscillator crystal input or an external
clock reference input.
Main oscillator crystal output.
GPIO port A bit 0
GPIO port A bit 1
July 26, 2008