IDT72V291L20PF IDT, Integrated Device Technology Inc, IDT72V291L20PF Datasheet - Page 17
![no-image](/images/manufacturer_photos/0/3/324/idt__integrated_device_technology_inc_sml.jpg)
IDT72V291L20PF
Manufacturer Part Number
IDT72V291L20PF
Description
IC FIFO SS 32768X36 20NS 64QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V281L15TF8.pdf
(26 pages)
Specifications of IDT72V291L20PF
Function
Synchronous
Memory Size
1.1M (32K x 36)
Data Rate
50MHz
Access Time
20ns
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Configuration
Dual
Density
1.125Mb
Access Time (max)
12ns
Word Size
9b
Organization
128Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
50MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Supply Current
55mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
72V291L20PF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V291L20PF
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Part Number:
IDT72V291L20PF
Manufacturer:
IDT
Quantity:
20 000
Company:
Part Number:
IDT72V291L20PF8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTES:
1. t
2. LD = HIGH.
3. First data word latency: 60ns + t
NOTES:
1. t
2. LD = HIGH, OE = LOW, EF = HIGH
Q
D
IDT72V281/72V291 3.3V CMOS SUPERSYNC FIFO
65,536 x 9 and 131,072 x 9
WCLK
RCLK
0
0
Q
WEN
D
of WCLK and the rising edge of RCLK is less than t
REN
edge of the RCLK and the rising edge of the WCLK is less than t
- Q
- D
SKEW3
SKEW1
WCLK
0
0
OE
RCLK
EF
WEN
REN
- D
- Q
n
n
FF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus t
n
n
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus t
t
ENS
t
DATA IN OUTPUT REGISTER
ENS
t
OLZ
t
ENH
t
t
SKEW1
REF
t
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
A
t
OE
REF
(1)
+ 1*T
t
SKEW3
t
ENS
t
ENH
t
DS
RCLK
D
t
(1)
A
0
1
.
NO OPERATION
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
NO WRITE
t
t
DHS
ENH
SKEW3
LAST WORD
1
, then EF deassertion may be delayed one extra RCLK cycle.
TM
2
SKEW1
t
WFF
, then the FF deassertion may be delayed one extra WCLK cycle.
t
OHZ
t
t
t
DS
ENS
DS
t
CLKH
D
1
D
NO OPERATION
X
t
WFF
t
t
ENH
DH
17
DATA READ
t
t
DH
CLK
2
t
t
CLKL
CLKH
t
REF
t
ENS
t
OLZ
t
SKEW1
t
CLK
(1)
t
CLKL
t
ENS
t
LAST WORD
ENH
t
A
1
NO WRITE
t
ENH
t
A
COMMERCIAL AND INDUSTRIAL
REF
WFF
2
). If the time between the rising edge
). If the time between the rising
TEMPERATURE RANGES
NEXT DATA READ
t
ENS
t
WFF
t
DS
D
0
D
X
+1
t
REF
t
t
ENH
A
4513 drw 10
t
DH
t
WFF
4513 drw 11
D
1