MT16VDDF12864HG-265 Micron, MT16VDDF12864HG-265 Datasheet - Page 12

• Manufacturer Part Number: MT16VDDF12864HG-265
• Description: 1GB DDR SDRAM SODIMM
• Manufacturer: Micron

Table 11:
PDF: 09005aef80a77a90/Source: 09005aef80a646bc
DDF16C64_128x64_L_H.fm - Rev. G 8/08 EN
Parameter/Condition
Operating one bank active-precharge current: One
device bank; Active-precharge;
(MIN); DQ, DM, and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two
clock cycles
Operating one bank active-read-precharge current:
One device bank; Active-read-precharge; BL = 4;
(MIN);
inputs changing once per clock cycle
Precharge power-down standby current: All device
banks idle; Power-down mode;
Idle standby current: CS# = HIGH; All device banks are idle;
t
inputs changing once per clock cycle. V
and DM
Active power-down standby current: One device bank
active; Power-down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One
device bank active;
DM, and DQS inputs changing twice per clock cycle; Address
and other control inputs changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst
reads; One device bank active; Address and control inputs
changing once per clock cycle;
Operating burst write current: BL = 2; Continuous burst
writes; One device bank active; Address and control inputs
changing once per clock cycle;
DQS inputs changing twice per clock cycle
Auto refresh burst current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device
bank interleaving READs (BL = 4) with auto precharge;
t
control inputs change only during active READ or WRITE
commands
CK =
RC = (MIN)
t
CK (MIN); CKE = HIGH; Address and other control
t
CK =
t
t
RC allowed;
CK (MIN); I
I
Values are shown for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
DD
Specifications and Conditions – 1GB
Notes:
t
RC =
OUT
t
t
CK = tCK (MIN); Address and
RAS (MAX);
t
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
3. The standard module guarantees I
CK =
= 0mA; Address and control
t
t
in I
t
CK =
t
CK =
RC =
CK =
t
CK (MIN); CKE = LOW
DD
t
2P (CKE LOW) mode.
t
t
CK (MIN); DQ, DM, and
t
CK (MIN); I
RC (MIN);
CK (MIN); CKE = (LOW)
t
IN
CK =
= V
t
t
Standard
Low power
REFC =
REFC = 7.8125µs
REF
t
CK (MIN); DQ,
for DQ, DQS,
t
OUT
CK =
t
RC =
t
RFC (MIN)
= 0mA
t
CK
t
RC
12
512MB, 1GB (x64, DR) 200-Pin DDR SODIMM
I
Symbol
I
DD
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
DD
DD
DD
DD
DD
DD
6A
4W
6
3N
5A
2P
3P
4R
2F
6 and the low power module guarantees I
0
1
5
7
2, 3
2, 3
1
1
2
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2
2
2
1
2
2
1
1,280
1,520
1,560
1,600
5,520
3,640
-40B
880
720
960
176
80
80
48
Electrical Specifications
1,080
1,320
1,360
1,440
4,640
3,280
-335
720
560
800
160
80
80
48
©2003 Micron Technology, Inc. All rights reserved
1,200
1,200
1,120
4,480
2,840
-265
960
640
480
720
160
90
80
48
DD
6A.
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA