MT16VDDF12864HG-40B Micron, MT16VDDF12864HG-40B Datasheet - Page 15

• Manufacturer Part Number: MT16VDDF12864HG-40B
• Description: DRAM Module, 128M x 64, 200-Pin DDR SDRAM SODIMM
• Manufacturer: Micron

Table 13: I
Notes: 1–5, 8, 10, 12, 48; DDR SDRAM devices only; notes appear on pages 18–20; 0°C £ T
09005aef80b577fa
DDAF16C64_128x64HG_A.fm - Rev. A 5/03 EN
PARAMETER/CONDITION
NOTE:
OPERATING CURRENT: One device bank; Active-Precharge;
(MIN);
cycle; Address and control inputs changing once every two clock cycles
OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst =
4;
inputs
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks are idle;
(MIN);
cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
active
twice per clock cycle; Address and other control inputs changing once per
clock cycle
OPERATING CURRENT: Burst = 2;
active; Address and control inputs changing once per clock cycle;
(MIN);
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank
t
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT: CKE £ 0.2V
OPERATING CURRENT: Four device bank interleaving READs
with auto precharge,
and control inputs change only during Active READ, or WRITE commands
CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle
t
a - Value calculated as one module rank in this operating condition, and all other module ranks in I
b - Value calculated reflects all module ranks in this operating condition.
RC =
;
active; Address and control inputs changing once per clock cycle;
I
CKE = HIGH; Address and other control inputs changing once per clock
t
t
changing once per clock cycle
OUT
IN
RC =
CK =
t
RC (MIN);
= V
= 0mA
t
t
REF
RAS (MAX);
CK (MIN); DQ, DM and DQS inputs changing once per clock
DD
for DQ, DQS, and DM
t
Specifications and Conditions – 1GB
CK =
t
t
t
CK =
CK =
RC = minimum
t
t
CK =
CK (MIN); I
t
t
CK (MIN); CKE = LOW
CK (MIN);
t
CK (MIN); DQ, DM and DQS inputs changing
Reads; Continuous burst; One device bank
t
OUT
RC allowed;
CKE = (LOW)
= 0mA; Address and control
t
CK =
t
t
t
One device bank
RC =
RFC = 7.8125µs
CK (MIN); Address
15
t
t
RFC (MIN)
RC =
(Burst = 4)
t
CK =
t
CK =
t
RC
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
t
CK
CK =
t
CK
512MB, 1GB (x64) PC3200
I
I
I
I
I
I
I
SYM
DD4W
DD3N
DD5A
I
I
DD4R
I
I
I
DD2P
DD2F
DD3P
DD0
DD1
DD5
DD6
DD7
200-PIN DDR SODIMM
A
£ +70°C; V
MAX
1,280
1,520
1,560
1,560
5,520
3,640
-40B
880
720
880
176
80
80
DD
DD
, V
2p (CKE LOW) mode.
UNITS
DD
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
©2003 Micron Technology, Inc.
Q = +2.6V ±0.1V
21, 28, 44
21, 28, 44
NOTES
20, 42
20, 42
20, 42
20, 44
24, 44
20, 43
45
41
20
9