CLAA150PB01 CHUNGHWA PICTURE TUBES, CLAA150PB01 Datasheet - Page 7

• Manufacturer Part Number: CLAA150PB01
• Description: Display Module
• Manufacturer: CHUNGHWA PICTURE TUBES

CPT
5. Input Signal Timing
CPT Confidential
(2) CN2 ( BACK LIGHT )
(1) CN1
(1) LVDS (Rx) Input Signal Timing Chart
[Note] EDID Inside
[Note] DDC : Display Data Requirements
[Note] Refer to page 6 ( Data Mapping )
pin
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
1
2
3
4
5
6
7
8
9
[Note] VBLH-VBLL = VL
Inverter-side connector : SM02B-BHSS-1(JST made)
Backlight-side connector : BHSR-02VS-1(JST made)
Connector type : FI-XB30S-HF10 (JAE made)
Corresponding connector type :
FI-X30M (JAE made , FPC type) , FI-X30H ( JAE made , wire )
CLKIN+( Even) Even Clock Signal(+)
( INTERFACE SIGNAL )
CLKIN-( Even) Even Clock Signal(-)
Link 0+( Even) LVDS Receiver Signal(+): Even R0-R5,G0
Link 1+( Even) LVDS Receiver Signal(+): Even G1-G5,B0-B1
Link 2+( Even) LVDS Receiver Signal(+): Even B2-B5
Pin No.
CLKIN+(Odd) Odd Clock Signal(+)
Link 1-( Even) LVDS Receiver Signal(-): Even G1-G5,B0-B1
Link 2-( Even) LVDS Receiver Signal(-): Even B2-B5
CLKIN-(Odd)
DATA_EDID
Link 0-(Even)
Link 0+(Odd)
Link 1+(Odd)
Link 2+(Odd)
Link 0-(Odd)
Link 1-(Odd)
Link 2-(Odd)
CLK_EDID
V_EDID
1
2
Symbol
GND
GND
GND
GND
GND
GND
GND
VCC
VCC
VSS
NC
Ground
+3.3V
+3.3V
DDC 3.3V Power
VCOM test provided , but customer-end unused (open)
DDC Clock
DDC Data
LVDS Receiver Signal(-): Odd R0-R5,G0
LVDS Receiver Signal(+): Odd R0-R5,G0
Ground
LVDS Receiver Signal(-): Odd G1-G5,B0-B1
LVDS Receiver Signal(+): Odd G1-G5,B0-B1
Ground
LVDS Receiver Signal(-): Odd B2-B5,HD,VD,DENA
LVDS Receiver Signal(+): Odd B2-B5,HD,VD,DENA
Ground
Odd Clock Signal(-)
Ground
LVDS Receiver Signal(-): Even R0-R5,G0
Ground
Ground
Ground
Symbol
CTH
CTL
[Note]
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www.DataSheet.net/
CHUNGHWA PICTURES TUBES, LTD.,
Function
VBLH (High voltage)
VBLL (Low voltage)
Function
CLAA150PB01--VER.1- 2004/9/16
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Datasheet pdf - http://www.DataSheet4U.co.kr/