IDT72V2111L10PFG IDT, Integrated Device Technology Inc, IDT72V2111L10PFG Datasheet - Page 24

• Manufacturer Part Number: IDT72V2111L10PFG
• Description: IC FIFO SS 512X9 10NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V2111L10PFG

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Other names: 72V2111L10PFG

NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 262,144 for the IDT72V2101 and 524,288 for the IDT72V2111.
2. For FWFT mode: D = maximum FIFO depth. D = 262,145 for the IDT72V2101 and 524,289 for the IDT72V2111.
WCLK
WCLK
IDT72V2101/72V2111 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
RCLK
RCLK
WEN
WEN
REN
REN
WCLK and the rising edge of RCLK is less than t
PAE
SKEW2
HF
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
t
CLKH
TM
262,144 x 9, 524,288 x 9
t
ENS
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
ENH
[
(2)
t
SKEW2
D-1
1
,
2
(3)
D/2 words in FIFO
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
SKEW2
+ 1
(4)
]
, then the PAE deassertion may be delayed one extra RCLK cycle.
words in FIFO
t
t
PAE
CLKH
(1)
2
,
(2)
t
ENS
t
CLKL
24
t
t
ENH
ENS
t
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
[
D/2 + 1 words in FIFO
t
D-1
ENH
2
+ 2
]
(2)
(3)
words in FIFO
,
t
HF
1
(1)
,
(2)
COMMERCIAL AND INDUSTRIAL
PAE
). If the time between the rising edge of
t
PAE
[
TEMPERATURE RANGES
D-1
2
D/2 words in FIFO
2
+ 1
]
words in FIFO
n words in FIFO
n+1 words in FIFO
4669 drw 21
4669 drw 20
(1)
,
(2)
(2)
,
(3)