MT9079 Mitel Semiconductor, MT9079 Datasheet - Page 35

• Manufacturer Part Number: MT9079
• Description: CMOS ST-BUS FAMILY Advanced Controller for E1
• Manufacturer: Mitel Semiconductor

2 - 0
Bit
Table 56 - Most Significant Phase Status Word
7
6
5
4
3
RxTS4-2
RSLPD
RxFRM
Name
RSLIP
AUXP
CEFS
(Page 3, Address 15H)
Receive Slip. A change of state (i.e.,
1-to-0 or 0-to-1) indicates that a
receive controlled frame slip has
occurred.
Receive Slip Direction. If one, indi-
cates that the last received frame slip
resulted in a repeated frame, i.e.,
system clock (C4i/C2i) faster than
network clock (ECLK). If zero, indi-
cates that the last received frame slip
resulted in a lost frame, i.e., system
clock slower than network clock.
Updated on an RSLIP occurrence
basis.
Auxiliary Pattern. This bit will go high
when a continuous 101010... bit
stream (Auxiliary Pattern) is received
on the PCM 30 link for a period of at
least 512 bits. If zero, auxiliary pat-
tern is not being received. This pat-
tern will be decoded in the presents
of a bit error rate of as much as 10
Consecutively Errored Frame Align-
ment Signal. This bit goes high when
the last two frame alignment signals
were received in error. This bit will be
low when at least one of the last two
frame alignment signals is without
error.
Receive Frame. The most significant
bit of the phase status word. If one,
the phase status word is greater than
one frame in length; if zero, the
phase status word is less than one
frame in length.
Receive Time Slot. The three most
significant bits of a five bit counter
that indicates the number of time
slots between the ST-BUS frame
pulse and E8Ko.
Functional Description
-3
.
7 - 6
5 - 3
2 - 0
Bit
Table 57 - Least Significant Phase Status Word
Bit
7
6
5
RxEBC2 -0 Receive Eighth Bit Count. A three bit
(Page 3, Address 19H) (continued)
RxBC2 -0
Table 58 - Alarm Status Word One
RxTS1-0
CRCS1
CRCS2
Name
Name
RFAIL
(Page 3, Address 16H)
Receive Time Slot. The two least sig-
nificant bits of a five bit counter that
indicates the number of time slots
between the ST-BUS frame pulse
and E8Ko.
Receive Bit Count. A three bit
counter that indicates the number of
bits between the ST-BUS frame
pulse and E8Ko.
counter that indicates the number of
one eighth bit times there are
between the ST-BUS frame pulse
and E8Ko. These least significant
bits are valid only when the device is
clocked at 4.096 MHz. The accuracy
of the this measurement is approxi-
mately + 1/16 (one sixteenth) of a bit.
Receive CRC Error Status One. If
one, the evaluation of the last
received submultiframe one resulted
in an error. If zero, the last submulti-
frame one was error free. Updated
on a submultiframe one basis.
Receive CRC Error Status Two. If
one, the evaluation of the last
received submultiframe two resulted
in an error. If zero, the last submulti-
frame two was error free. Updated on
a submultiframe two basis.
Remote CRC-4 Multiframe Genera-
tor/detector Failure. If one, each of
the previous five seconds have an
E-bit error count of greater than 989,
and for this same period the receive
RAI bit was zero (no remote alarm),
and for the same period the SYNC bit
was equal to zero (basic frame align-
ment has been maintained). If zero,
indicates normal operation.
Functional Description
Functional Description
MT9079
4-271