MT9085BPR Zarlink Semiconductor, Inc., MT9085BPR Datasheet
MT9085BPR
Manufacturer Part Number
MT9085BPR
Description
1024 Channels TDM (ST-BUS) to Parallel Bus Access Circuit (PAC)
Manufacturer
Zarlink Semiconductor, Inc.
Datasheet
1.MT9085BPR.pdf
(20 pages)
Features
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Applications
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S30
S31
Configurable for parallel-to-serial or
serial-to-parallel conversion of 1024 channels
Supports serial data rates of 2.048 Mbit/s or
4.096 Mbit/s
Interfaces to Zarlink’s MT9080 Switch Matrix
Module (SMX)
Generates all framing signals required in 1K or
2K switching applications
Expandable to 2048ch. systems
Compatible to ST-BUS
Custom designed small and medium digital
switch matrices using Zarlink MT9080B
Rate conversion applications
Interfacing a parallel system bus to devices
utilizing serial I/O
Telephony:PBX, CO, digital cross connects,
digital local loop
Datacom: Integrated Access Concentrators,
WAN/LAN gateways
S0
S1
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Parallel/Serial
Registers
Shift
LOAD
C16
C4
Figure 1 - Functional Block Diagram
VSS
Address
Decoder
VDD
DS5141
Description
The MT9085 Parallel Access Circuit (PAC) provides
an interface between an 8 bit, parallel time division
multiplexed bus and a serial time division multiplexed
bus. A single PAC device will accept data clocked out
on the parallel bus of the Zarlink MT9080 (SMX) and
output it on 32/16 time division multiplexed serial bus
streams. A second device can be configured to
perform the conversion from the serial format into an
SMX compatible parallel format. The time division,
serial multiplexed streams may operate at 2.048
Mbit/s or at 4.096 Mbit/s. The PAC generates all
framing signals required by the SMX for 1024 and
2048 channel configurations.
PAC - Parallel Access Circuit
MT9085BP
C16
C4
Ordering Information
-40 ° C to 70 ° C
Generation
Control
Timing
Mode
ISSUE 4
68 Pin PLCC
MT9085B
March 1999
P0
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P7
C4i
F0i
C16i
C2o
C4o
F0o
DFPo
DFPo
CFPo
OE
MCA
MCB
CKD
2/4S
2-125
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