IDT72V2113L7-5BC IDT, Integrated Device Technology Inc, IDT72V2113L7-5BC Datasheet - Page 43
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IDT72V2113L7-5BC
Manufacturer Part Number
IDT72V2113L7-5BC
Description
IC FIFO SUPERSYNCII 7-5NS 100BGA
Manufacturer
IDT, Integrated Device Technology Inc
Series
72Vr
Datasheet
1.IDT72V2103L15PF8.pdf
(46 pages)
Specifications of IDT72V2113L7-5BC
Function
Synchronous
Memory Size
4.7Mb (262k x 18)
Access Time
5ns
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-LBGA
Configuration
Dual
Density
4.5Mb
Access Time (max)
5ns
Word Size
18/9Bit
Organization
256Kx18/512Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3.15V
Operating Supply Voltage (max)
3.45V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Rate
-
Lead Free Status / RoHS Status
Not Compliant, Contains lead / RoHS non-compliant
Other names
72V2113L7-5BC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT72V2113L7-5BC
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
Company:
Part Number:
IDT72V2113L7-5BCI
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
NOTE:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
1149.1) for the full state diagram.
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the Queue and must be reset after power up of the device. See TRST
description for more details on TAP controller reset.
the normal operation of the IC. The TAP controller state machine is designed
in such a way that, no matter what the initial state of the controller is, the Test-
Logic-Reset state can be entered by holding TMS at high and pulsing TCK five
times. This is the reason why the Test Reset (TRST) pin is optional.
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Data Path or the Select-IR-Scan state is made.
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
IDT72V263/273/283/293/103/113 3.3V HIGH DENSITY SUPERSYNC II
8K x 18, 16K x 9/18, 32K x 9/18, 64K x 9/18, 128K x 9/18, 256K x 9/18, 512K x9
IDT72V2103/72V2113 3.3V HIGH DENSITY SUPERSYNC II
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9
Run-Test-Idle In this controller state, the test logic in the IC is active only if
Select-DR-Scan This is a controller state where the decision to enter the
Select-IR-Scan This is a controller state where the decision to enter the
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
All state transitions within the TAP controller occur at the rising edge of the
Test-Logic-Reset All test logic is disabled in this controller state enabling
Input = TMS
1
0
Test-Logic
Run-Test/
Reset
Idle
0
Figure 33. TAP Controller State Diagram
TM
1
NARROW BUS FIFO
1
0
1
Update-DR
Capture-DR
Pause-DR
Exit2-DR
DR-Scan
Exit1-DR
Shift-DR
Select-
TM
43
0
NARROW BUS FIFO
0
0
1
1
1
0
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be “01”.
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
IR state or Update-IR state is made.
register to be temporarily halted.
IR state or Update-IR state is made.
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
registers selected by the current instruction on the rising edge of TCK.
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
0
Capture-IR In this controller state, the shift register bank in the Instruction
Shift-IR In this controller state, the instruction register gets connected
Exit1-IR This is a controller state where a decision to enter either the Pause-
Pause-IR This state is provided in order to allow the shifting of instruction
Exit2-DR This is a controller state where a decision to enter either the Shift-
Update-IR In this controller state, the instruction in the instruction register is
Capture-DR In this controller state, the data is parallel loaded in to the data
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
0
1
1
0
1
1
1
1
1
Capture-IR
Update-IR
Pause-IR
Exit2-IR
IR-Scan
Exit1-IR
Shift-IR
Select-
1
0
0
0
0
6119 drw36
0
0
1
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JUNE 1, 2010