IDT72T20128L6-7BB IDT, Integrated Device Technology Inc, IDT72T20128L6-7BB Datasheet - Page 16

• Manufacturer Part Number: IDT72T20128L6-7BB
• Description: IC FIFO 1KX20 2.5V 6-7NS 208BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Tr

Specifications of IDT72T20128L6-7BB

• Function: Synchronous
• Memory Size: 20K (1K x 20)
• Access Time: 3.8ns
• Voltage - Supply: 2.375 V ~ 2.625 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 208-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Other names: 72T20128L6-7BB

RETRANSMIT FROM MARK OPERATION
starting at a user-selected position. The FIFO is first put into retransmit mode
that will “mark” a beginning word and also set a pointer that will prevent
ongoing FIFO write operations from over-writing retransmit data. The retrans-
mit data can be read repeatedly any number of times from the “marked”
position. The FIFO can be taken out of retransmit mode at any time to allow
normal device operation. The “mark” position can be selected any number of
times, each selection over-writing the previous mark location.
read on the rising and falling edge of WCLK. If the data marked was read on
the falling edge of RCLK, then the marked data will be the unit of data read from
the rising and falling edge of that particular RCLK edge. Refer to Figure 23,
Retransmit from Mark in Double Data Rate Mode, for the timing diagram in
this mode. Retransmit operation is available in both IDT standard and FWFT
modes.
to-High transition on RCLK when the MARK input is HIGH and EF is HIGH.
The rising RCLK edge marks the data present in the FIFO output register as
the first retransmit data. Again, the data is marked in pairs. Thus if the data
marked was read on the falling edge of RCLK, the first part of retransmit will
read out the data read on the rising edge of RCLK, followed by the data on the
falling edge (the marked data). The FIFO remains in retransmit mode until a
rising edge on RCLK occurs while MARK is LOW.
rising edge on RCLK while the Retransmit input (RT) is LOW. REN must be
HIGH (reads disabled) before bringing RT LOW. The device indicates the start
of retransmit setup by setting EF LOW, also preventing reads. When EF goes
HIGH, retransmit setup is complete and read operations may begin starting
with the first unit of data at the MARK location. Since IDT standard mode is
selected, every word read including the first “marked” word following a re-
transmit setup requires a LOW on REN.
however write operations to the “marked” location will be prevented. See Figure
TABLE 6 — I/O CONFIGURATION
IDT72T2098/108/118/128 2.5V HIGH-SPEED TeraSync™ DDR/SDR FIFO 20-BIT/10-BIT CONFIGURATIONS
32K x 20/64K x 10, 64K x 20/128K x 10, 128K x 20/256K x 10, 256K x 20/512K x 10
The Retransmit from Mark feature allows FIFO data to be read repeatedly
In Double Data Rate, data is always marked in pairs. That is, the unit of data
During IDT standard mode the FIFO is put into retransmit mode by a Low-
Once a marked location has been set, a retransmit can be initiated by a
Note, write operations may continue as normal during all retransmit functions,
HIGH = HSTL
LOW = LVTTL
Write Port
Dn (I/P)
WCLK (I/P)
WEN (I/P)
WCS (I/P)
Qn (O/P)
RCLK (I/P)
REN (I/P)
RCS (I/P)
MARK (I/P)
OE (I/P)
RT (I/P)
Read Port
EF/OR (O/P)
PAF (O/P)
PAE (O/P)
FF/IR (O/P)
ERCLK (O/P)
EREN (O/P)
HSTL SELECT
16
SCLK (I/P)
SI (I/P)
SO (O/P)
MRS (I/P)
PRS (I/P)
TCK (I/P)
TMS (I/P)
23, Retransmit from Mark in Double Data Rate Mode, for the relevant timing
diagram.
edge when the MARK input is HIGH and OR is LOW. The rising RCLK edge
marks the data present in the FIFO output register as the first retransmit data.
The data is marked in pairs. The FIFO remains in retransmit mode until a
rising RCLK edge occurs while MARK is LOW.
rising RCLK edge while the Retransmit input (RT) is LOW. REN must be
HIGH (reads disabled) before bringing RT LOW. The device indicates the
start of retransmit setup by setting OR HIGH, preventing read operations.
RCLK edge (RT goes HIGH), the contents of the first retransmit location are
loaded onto the output register. Since FWFT mode is selected, the first word
appears on the outputs regardless of REN, a LOW on REN is not required for
the first word. Reading all subsequent words requires a LOW on REN to
enable the rising RCLK edge. See Figure 24, Retransmit from Mark (FWFT
mode) for the relevant timing diagram.
160 bytes) of data between the write pointer and mark location.That is, 20 bits
x64 for the x20 mode and 10 bits x128 for the x10 mode. Also, once the Mark
is set, the write pointer will not increment past the marked location, preventing
overwrites of retransmit data.
HSTL/LVTTL I/O
output signals. If LVTTL is desired, a LOW on the HSTL pin will set the inputs
and outputs to LVTTL mode. If HSTL is desired, a HIGH on the HSTL pin will
set the inputs and outputs to HSTL mode. VREF is the input voltage reference
used in HSTL mode. Typically a logic HIGH in HSTL would be Vref + 0.2V and
a logic LOW would be VREF – 0.2V. Table 6 illustrates which pins are and are
not associated with this feature. Note that all “Static Pins” must be tied to Vcc or
GND. These pins are LVTTL only and are purely device configuration pins.
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
Once a marked location has been set, a retransmit can be initiated by a
When OR goes LOW, retransmit setup is complete and on the next rising
Before a retransmit can be performed, there must be at least 1280 bits (or
This device supports both LVTTL and HSTL logic levels on the input and
Signal Pins
TRST (I/P)
TDI (I/P)
TDO (O/P)
SEN (I/P)
SREN (I/P)
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
LVTTL ONLY
Static Pins
IW (I/P)
OW (I/P)
HSTL (I/P)
FSEL1 (I/P)
FSEL0 (I/P)
FWFT (I/P)
WSDR (I/P)
RSDR (I/P)
FEBRUARY 13, 2009
STATIC PINS