CS4270 Cirrus Logic, CS4270 Datasheet - Page 36

• Manufacturer Part Number: CS4270
• Description: 192 kHz Stereo Audio CODEC
• Manufacturer: Cirrus Logic

36
8.4.2 ADC HPF Freeze B (Bit 6)
8.4.3 Digital Loopback (Bit 5)
8.4.4 DAC Digital Interface Format (Bits 4:3)
8.4.5 ADC Digital Interface Format (Bit 0)
DAC_DIF1 DAC_DIF0
ADC_DIF
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled.The current DC
offset value will be frozen and continuously subtracted from the conversion result.
Pass Filter and DC Offset Calibration” on page
Function:
When this bit is set, an internal digital loopback from the ADC to the DAC will be enabled. Please refer to
Section 5.2.5 “Internal Digital Loopback” on page
Function:
The DAC Digital Interface Format and the options are detailed in
Function:
The required relationship between LRCK, SCLK and SDOUT for the ADC is defined by the ADC Digital
Interface Format. The options are detailed in
0
1
0
0
1
1
0
1
0
1
Left Justified, up to 24-bit data (default)
Left Justified, up to 24-bit data (default)
I²S, up to 24-bit data
Table 10. DAC Digital Interface Formats
Table 11. ADC Digital Interface Formats
Description
Right Justified, 16-bit Data
Right Justified, 24-bit Data
I²S, up to 24-bit data
Description
Table 11
26.
26.
and may be seen in
Table 10
Format
0
1
Format
0
1
2
3
and Figures
Figures 5
www.DataSheet4U.com
Section 5.2.7 “High-
and 6.
Figure
Figure
5
5
6
7
7
through 7.
5
6
CS4270
DS686A1