CS43L42 Cirrus Logic, CS43L42 Datasheet - Page 28

• Manufacturer Part Number: CS43L42
• Description: Stereo DAC
• Manufacturer: Cirrus Logic

DIF1 and DIF0
(Stand-Alone Mode)
N.C.
CP/SA
VQ_HP
REF_GND
FILT+
VQ_LINE
HP_A and HP_B
GND
VA
VA_LINE
VA_HP
AOUTA and AOUTB
MUTEC
28
16 and 21
22 and 23
8 and 9
10
11
12
13
14
15
17
18
19
20
24
Digital Interface Format (Input) - The required relationship between the Left/Right clock,
No Connection - This pin has no internal connection to the device.
Mode Select (Input) - The Mode Select pin is used to select control port or stand-alone
Headphone Quiescent Voltage (Output) - Filter connection for internal headphone amp
Reference Ground (Input) - Ground reference for the internal sampling circuits. Must be
Positive Voltage Reference (Output) - Positive reference for internal sampling circuits. An
Line Out Quiescent Voltage (Output) - Filter connection for internal line amp quiescent ref-
Headphone Outputs (Output) - The full scale analog headphone output level is specified in
Ground (Input) - Ground Reference. Should be connected to analog ground.
Analog Power (Input) - Analog power supply. Typically 1.8 to 3.3 VDC.
Line Amp Power (Input) - Line amplifier power supply. Typically 1.8 to 3.3 VDC.
Note:
Headphone Amp Power (Input) - Headphone amplifier power supply. Typically 0.9 to
Analog Outputs (Output) - The full scale analog line output level is specified in the Analog
Mute Control (Output) - The Mute Control pin goes high during power-up initialization, re-
serial clock and serial data is defined by the Digital Interface Format and the options are de-
tailed in Figures 26-29.
mode. When high, the CS43L42 will operate in control port mode. When low, the CS43L42
will operate in stand-alone mode.
quiescent reference voltage. A capacitor must be connected from VQ_HP to analog ground,
as shown in Figure 6. VQ_HP is not intended to supply external current. VQ_HP has a typ-
ical source impedance of 250 kΩ and any current drawn from this pin will alter device per-
formance.
connected to analog ground.
external capacitor is required from FILT+ to analog ground, as shown in Figure 6. The rec-
ommended value will typically provide 60 dB of PSRR at 1 kHz and 40 dB of PSRR at 60 Hz.
FILT+ is not intended to supply external current. FILT+ has a typical source impedance of
250 kΩ and any current drawn from this pin will alter device performance.
erence voltage. A capacitor must be connected from VQ_LINE to analog ground, as shown
in Figure 6. VQ_LINE is not intended to supply external current. VQ_LINE has a typical
source impedance of 250 kΩ and any current drawn from this pin will alter device perfor-
mance.
the Analog Characteristics specifications table.
3.3 VDC.
Characteristics specifications table.
set, muting, power-down or if the master clock to left/right clock frequency ratio is incorrect.
This pin is intended to be used as a control for an external mute circuit on the line outputs
to prevent the clicks and pops that can occur in any single supply system. Use of Mute Con-
trol is not mandatory but recommended for designs requiring the absolute minimum in ex-
traneous clicks and pops.
DIF1
Table 12. Digital Interface Format - DIF1 and DIF0 (Stand-Alone Mode)
0
0
1
1
If the line outputs are not used, connect VA_LINE to VA.
DIF0
0
1
0
1
I
Left Justified, up to 24-bit data
Right Justified, 24-bit Data
Right Justified, 16-bit Data
2
S, up to 24-bit data
DESCRIPTION
FORMAT
0
1
2
3
FIGURE
CS43L42
26
27
28
29
DS481PP2