LP365 National Semiconductor, LP365 Datasheet - Page 3

• Manufacturer Part Number: LP365
• Description: Micropower Programmable Quad Comparator
• Manufacturer: National Semiconductor

Symbol
V
I
I
A
V
CMRR
PSRR
I
V
V
I
I
t
OS
B
S
SINK
LEAK
R
Electrical Characteristics
Note 1 The input voltage is not allowed to go 0 3V above V
the device
Note 2 Short circuits from the output to V
allowed to exceed 30 mA The output should not be shorted to V
Note 3 For operating at elevated temperatures these devices must be derated based on a thermal resistance of
Note 4 Boldface numbers apply at temperature extremes All other numbers apply at T
V
Note 5 Guaranteed and 100% production tested
Note 6 Guaranteed (but not 100% production tested) over the operating temperature and supply voltage ranges These limits are not used to calculate out-going
quality levels
Note 7 The response time specified is for a 100 mV input step with 5 mV overdrive
Note 8 Boldface numbers apply at temperature extremes All other numbers apply at T
V
Note 9 See AN-450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ for other methods of soldering surface mount devices
Note 10 Human body model 1 5 k
OS
VOL
CM
OH
OL
C
C
e
e
5V as shown in the Typical Connection diagram
5V as shown in the Typical Connection diagram
Input Offset
Voltage
Input Offset
Current
Input Bias
Current
Large Signal
Voltage Gain
Input Common-
Mode Voltage
Range
Common-Mode
Rejection Ratio
Supply Voltage
Rejection Ratio
Supply Current
Output Voltage
High
Output Voltage
Low
Output Sink
Current
Output Leakage
Current
Response Time
Parameter
in series with 100 pF
V
R
V
LP265
V
LP265
R
b
s
s g
All Inputs
R
V
V
R
V
V
V
V
V
V
V
R
C
(Note 7)
g
a
CM
CM
CM
C
E
E
E
O
C
E
CC
E
S
L
L
L
L
L
Conditions
13V
10V
15V
may cause excessive heating and eventual destruction The current in the output leads and the V
e
e
e
e
e
e
eb
e
e
e
e
e
e
e
15V
e
e
e
e
10 pF
15k
% LP265
5V
0V
100k
0V
0V
15V
0V
5k
100
0 4V
s
s
5V
0V
0V
0V
15V
V
V
e
S
CM
(Continued) (Note 8) High power V
0V
a
or
b
b
Typ
500
2 6
1 0
60
85
80
10
1
5
5
0 3V below V
if V
E s
(V
(Note 5)
b
Tested
Limit
)
b
LP365A
200
100
3
4 9
0 4
50
13
75
70
50
a
b
3
3
8
15
7V
as this will turn on a parasitic transistor causing large currents to flow through
A
e
(Note 6)
Design
T
5000
Limit
b
j
100
500
100
e
3 3
4 5
0 4
5 5
13
70
70
6
S
15
25 C V
A
e
e
T
g
j
e
15V I
a
25 C V
e a
Typ
500
2 8
2 8
7 5
1 0
10
10
80
80
80
75
3
5
SET
15V V
a
e
jA
e
5V V
and T
b
100 A
(Note 5)
Tested
eb
Limit
b
300
300
100
3 5
3 5
4 9
0 4
b
90
90
13
75
70
50
LP365
j
6
6
15
max T
e
15V I
0V I
SET
SET
j
e
T
e
e
A
(Note 6)
Design
100 A R
5000
a
10 A R
Limit
b
200
500
500
800
100
3 7
4 3
4 5
0 4
13
70
70
E
9
4
15
jA
lead should not be
P
D
L
L
e
e
100k and
100k and
(Limit)
V mV
Units
(Max)
(Max)
(Max)
(Max)
(Max)
(Max)
(Max)
(Min)
(Min)
(Min)
(Min)
(Min)
(Min)
mV
mA
mA
nA
nA
dB
dB
nA
V
V
V
V
s