CY7C4211-15AC Cypress Semiconductor Corp, CY7C4211-15AC Datasheet - Page 10

• Manufacturer Part Number: CY7C4211-15AC
• Description: IC SYNC FIFO MEM 512X9 32-TQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4211-15AC

• Function: Synchronous
• Memory Size: 4.6K (512 x 9)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP
• Configuration: Dual
• Density: 4Kb
• Access Time (max): 10ns
• Word Size: 9b
• Organization: 512x9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1211

Document #: 38-06016 Rev. *C
Switching Waveforms
Reset Timing
First Data Word Latency after Reset with Simultaneous Read and Write
Notes:
WEN2/LD
17. The clocks (RCLK, WCLK) can be free-running during reset.
18. Holding WEN2/LD HIGH during reset will make the pin act as a second enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable
19. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
20. When t
21. The first word is available the cycle after EF goes HIGH, always.
for the programmable flag offset registers.
t
CLK
Q
EF,PAE
FF,PAF,
+ t
REN1,
WEN1
0 -
REN2
SKEW1
SKEW1
RS
[18]
Q
(if applicable)
8
. The Latency Timing applies only at the Empty Boundary (EF = LOW).
> minimum specification, t
[17]
D
Q
WEN2
WCLK
WEN1
REN1,
RCLK
REN2
0
0
–D
–Q
OE
EF
8
8
t
ENS
t
DS
(continued)
D
0 (FIRST
FRL
(maximum) = t
VALID
t
t
t
t
RSF
RSF
RSF
SKEW1
t
Write)
RS
t
t
t
t
OLZ
t
RSS
RSS
RSS
CLK
FRL
[20]
+ t
SKEW1
t
D
REF
1
. When t
SKEW1
t
OE
< minimum specification, t
t
A
D
[21]
2
t
t
t
RSR
RSR
RSR
CY7C4421/4201/4211/4221
CY7C4231/4241/4251
D
FRL
0
D
t
(maximum) = either 2*t
A
3
D
OE = 0
OE = 1
1
D
4
Page 10 of 19
CLK
[19]
+ t
SKEW1
or
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