CY7C4261-15JXC Cypress Semiconductor Corp, CY7C4261-15JXC Datasheet
CY7C4261-15JXC
Specifications of CY7C4261-15JXC
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CY7C4261-15JXC Summary of contents
Page 1
... WCLK cycle. The output port is controlled in a similar manner by a free running read clock (RCLK) and two read enable pins (REN1, REN2). In addition, the CY7C4261/71 has an output enable pin (OE). The read (RCLK) and write (WCLK) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write applications ...
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... CONTROL WRITE POINTER RESET RS LOGIC Document #: 38-06015 Rev 0–8 INPUT REGISTER WEN2/ LD RAM ARRAY 16K x 9 32K x 9 THREE-STATE OUTPUT REGISTER OE Q RCLK 0–8 CY7C4261, CY7C4271 FLAG PROGRAM REGISTER EF FLAG PAE LOGIC PAF FF READ POINTER READ CONTROL REN1 REN2 Page [+] Feedback ...
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... HIGH, the FIFO’s outputs are in High Z (high impedance) state. Document #: 38-06015 Rev. *F Figure 2. Pin Diagram - 32-Pin TQFP (Top View WEN1 D 0 WCLK PAF LD WEN2/ PAE V CC GND REN1 7 Q RCLK REN2 Description CY7C4261, CY7C4271 WEN1 2 23 WCLK 3 WEN2/LD 22 CY7C4261 CY7C4271 ...
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... Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Architecture The CY7C4261/71 consists of an array of 16K to 32K words of nine bits each (implemented by a dual port array of SRAM cells), a read pointer, a write pointer, control signals (RCLK, WCLK, REN1, REN2, WEN1, WEN2, RS), and flags (EF, PAE, PAF, FF) ...
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... FF). The partial status flags (PAE and PAF) can be detected from any one device. Selection a 18-bit word width by using two CY7C4261/71s. Any word width can be attained by adding additional CY7C4261/71s. When the CY7C4261/ Width Expansion Configuration, the Read Enable (REN2) control input can be grounded (see Figure 4 on page 6) ...
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... WRITE ENABLE 2/LOAD (WEN2/LD) PROGRAMMABLE(PAF) FULL FLAG (FF FULL FLAG (FF Read Enable 2 (REN2) Document #: 38-06015 Rev. *F RESET (RS) RESET (RS) 9 CY7C4261/71 CY7C4261/ Read Enable 2 (REN2) CY7C4261, CY7C4271 READ CLOCK (RCLK) READ ENABLE 1 (REN1) OUTPUT ENABLE (OE) PROGRAMMABLE(PAE) EMPTY FLAG (EF) #1 EMPTY FLAG (EF DATA OUT ( Page [+] Feedback ...
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... OE + < V < Com’l 35 Ind/Mil 40 Com’l 10 Ind/Mil 15 Test Conditions MHz 5.0V CC CY7C4261, CY7C4271 Ambient Temperature V CC 5V 10 +70 C 40 5V 10 +85 C 55 5V 10 +125 C Max Min Max Min Max 2.4 2.4 ...
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... Figure 5. AC Test Loads and Waveforms R1 1.1K 3.0V GND R2 680 1.91V 7C4261/71-10 7C4261/71-15 Min Max Min 100 4 [13 [13 CY7C4261, CY7C4271 [10, 11] ALL INPUT PULSES 90% 90% 10% 10% 3 ns 7C4261/71-25 7C4261/71- 35 Max Min Max Min Max 66 ...
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... NO OPERATION t REF t A VALID DATA t OE [15] t SKEW1 , then FF may not change state until the next WCLK rising edge. SKEW1 , then EF may not change state until the next RCLK rising edge. SKEW2 CY7C4261, CY7C4271 NO OPERATION NO OPERATION t WFF t REF t OHZ Page [+] Feedback ...
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... The first word is available the cycle after EF goes HIGH, always. Document #: 38-06015 Rev. *F [16] Figure 8. Reset Timing RSS t t RSS t t RSS t RSF t RSF t RSF [19] t FRL t SKEW1 t REF [20 OLZ When t < minimum specification, t CLK SKEW2 SKEW2 CY7C4261, CY7C4271 RSR RSR RSR [17 (maximum) = either 2 FRL CLK SKEW1 Page CLK [+] Feedback ...
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... Document #: 38-06015 Rev. *F Figure 10. Empty Flag Timing [19 REF REF t A Figure 11. Full Flag Timing t DS DATA WRITE t WFF t ENH t A DATA READ CY7C4261, CY7C4271 DATA WRITE 2 t ENH ENS t ENH ENS [19] t FRL t t REF SKEW1 DATA READ NO WRITE [14] DATA WRITE t SKEW1 t WFF t ...
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... If a write is performed on this rising edge of the write clock, there are Full (m1) words of the FIFO when PAF goes LOW. 25. PAF offset = m. 26. 16,384 m words for CY7C4261, 32,768 m words for CY7C4271. 27 the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of ...
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... Figure 14. Write Programmable Registers t CLKL t ENH t DH PAE OFFSET PAF OFFSET LSB MSB Figure 15. Read Programmable Registers t CLKL t ENH t A UNKNOWN PAE OFFSET LSB CY7C4261, CY7C4271 PAF OFFSET LSB MSB PAF OFFSET MSB PAF OFFSET PAE OFFSET MSB LSB Page [+] Feedback ...
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... AMBIENT TEMPERATURE ( C) NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE 1.20 1.10 1. 3. MHz 0.80 55.00 5.00 65.00 125.00 AMBIENT TEMPERATURE ( C) CY7C4261, CY7C4271 vs. AMBIENT 5.0V CC 5.00 65.00 125.00 NORMALIZED SUPPLY CURRENT vs. FREQUENCY 1.75 1.50 1. 3.0V IN 0.50 20 ...
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... Ordering Information 16 K × 9 Deep Sync FIFO Speed (ns) Ordering Code Package Diagram 10 CY7C4261-10JXI 15 CY7C4261-15JXC 32 K × 9 Deep Sync FIFO Speed (ns) Ordering Code Package Diagram 15 CY7C4271-15AXC Ordering Code Definitions CY7C 42X1 - Table 4. DC Characteristics Parameters Max CC1 SB1 SB2 Document #: 38-06015 Rev. *F ...
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... RFF t 9, 10, 11 WEF t 9, 10, 11 WFF t 9, 10, 11 WHF t 9, 10, 11 RHF t 9, 10, 11 RAE t 9, 10, 11 RPE t 9, 10, 11 WAF t 9, 10, 11 WPF t 9, 10, 11 XOL t 9, 10, 11 XOH Document #: 38-06015 Rev. *F Subgroups CY7C4261, CY7C4271 Page [+] Feedback ...
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... Package Diagrams Figure 17. 32-Pin Thin Plastic Quad Flatpack (7 × 7 × 1.0 mm) Document #: 38-06015 Rev. *F CY7C4261, CY7C4271 51-85063 *C Page [+] Feedback ...
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... Document #: 38-06015 Rev. *F Figure 18. 32-Pin Plastic Leaded Chip Carrier CY7C4261, CY7C4271 51-85002 *C Page [+] Feedback ...
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... Figure 19. 32-Pin Rectangular Leadless Chip Carrier Document #: 38-06015 Rev. *F CY7C4261, CY7C4271 51-80068 *A Page [+] Feedback ...
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... Switching Waveforms section: changed t Timing” drawing See ECN Added Pb-Free Logo to top of front page Added CY7C4261-10JXI, CY7C4261-15JXC to ordering information 08/22/2008 Updated ordering information and data sheet template. Removed Pb-Free Logo. 03/19/2010 Updated package diagrams Removed inactive parts from Ordering information table ...
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... Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06015 Rev. *F All products and company names mentioned in this document may be the trademarks of their respective holders. cypress.com/go/plc Revised October 13, 2010 CY7C4261, CY7C4271 PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 ...