CY7C4251-15JXC Cypress Semiconductor Corp, CY7C4251-15JXC Datasheet - Page 11
![IC SYNC FIFO MEM 8KX9 32-PLCC](/photos/6/51/65138/428-32-plcc_sml.jpg)
CY7C4251-15JXC
Manufacturer Part Number
CY7C4251-15JXC
Description
IC SYNC FIFO MEM 8KX9 32-PLCC
Manufacturer
Cypress Semiconductor Corp
Series
CY7Cr
Specifications of CY7C4251-15JXC
Function
Synchronous
Memory Size
72K (8K x 9)
Data Rate
100MHz
Access Time
10ns
Voltage - Supply
3.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-PLCC
Configuration
Dual
Density
64Kb
Access Time (max)
15ns
Word Size
9b
Organization
8Kx9
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Clock Freq (max)
40MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
35mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C4251-15JXC
Manufacturer:
ONSEMI
Quantity:
5 469
Company:
Part Number:
CY7C4251-15JXC
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Company:
Part Number:
CY7C4251-15JXCT
Manufacturer:
Cypress Semiconductor Corp
Quantity:
10 000
Switching Waveforms
Document #: 38-06016 Rev. *D
REN1,REN2
Notes
14. t
15. t
(if applicable)
REN1,REN2
the rising edge of RCLK and the rising edge of WCLK is less than t
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
SKEW1
WEN2
Q
D
WCLK
WEN1
WEN1
WEN2
WCLK
RCLK
0
RCLK
0
–Q
–D
OE
FF
EF
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF goes HIGH during the current clock cycle. If the time between
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF goes HIGH during the current clock cycle. It the time between
8
8
t
ENS
t
OLZ
t
SKEW1
t
ENH
[14]
t
t
CLKH
CLKH
t
t
t
WFF
A
REF
t
OE
t
t
CLK
CKL
t
Figure 5. Write Cycle Timing
Figure 6. Read Cycle Timing
SKEW1
NO OPERATION
SKEW1
SKEW1
[15]
t
DS
t
t
CLKL
CLKL
, then FF may not change state until the next WCLK rising edge.
, then EF may not change state until the next RCLK rising edge.
t
ENS
t
VALID DATA
DH
t
ENH
t
REF
t
WFF
CY7C4421/4201/4211/4221
t
OHZ
NO OPERATION
NO OPERATION
CY7C4231/4241/4251
Page 11 of 20
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