ST62E01C ST Microelectronics, ST62E01C Datasheet - Page 28

• Manufacturer Part Number: ST62E01C
• Description: (ST62T00C / ST62T01C / ST62T03C / ST62E01C) 8-BIT OTP/EPROM MCUs
• Manufacturer: ST Microelectronics

ST62T00C/T01C ST62T03C/E01C
INTERRUPTS (Cont’d)
3.4.3 Interrupt Option Register (IOR)
The Interrupt Option Register (IOR) is used to en-
able/disable the individual interrupt sources and to
select the operating mode of the external interrupt
inputs. This register is write-only and cannot be
accessed by single-bit operations.
Address: 0C8h — Write Only
Reset status: 00h
Bit 7, Bits 3-0 = Unused .
Bit 6 = LES: Level/Edge Selection bit .
When this bit is set to one, the interrupt source #1
is level sensitive. When cleared to zero the edge
sensitive mode for interrupt request is selected.
Table 8. Interrupt Requests and Mask Bits
*Except ST62T03C
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GENERAL
TIMER
A/D CONVERTER(*)
Port PAn
Port PBn
7
-
Peripheral
LES
ESB
GEN
IOR
TSCR
ADCR
ORPA-DRPA
ORPB-DRPB
Register
-
-
C8h
D4h
D1h
C4h-CCh
C5h-CDh
Address
Register
-
0
-
GEN
ETI
EAI
ORPAn-DRPAn
ORPBn-DRPBn
Mask bit
Bit 5 = ESB: Edge Selection bit .
The bit ESB selects the polarity of the interrupt
source #2.
Bit 4 = GEN: Global Enable Interrupt . When this bit
is set to one, all interrupts are enabled. When this
bit is cleared to zero all the interrupts (excluding
NMI) are disabled.
When the GEN bit is low, the NMI interrupt is ac-
tive but cannot cause a wake up from STOP/WAIT
modes.
This register is cleared on reset.
3.4.4 Interrupt sources
Interrupt sources available on the ST62E01C/
T01C are summarized in the Table 8 with associ-
ated mask bit to enable/disable the interrupt re-
quest.
All Interrupts, excluding
NM
TMZ: TIMER Overflow
EOC: End of Conversion
PAn pin
PBn pin
Masked Interrupt Source
I
Vector 3
Vector 4
Vector 1
Vector 2
Interrupt
vector