CY7C4255-10AXCT Cypress Semiconductor Corp, CY7C4255-10AXCT Datasheet - Page 2

• Manufacturer Part Number: CY7C4255-10AXCT
• Description: IC SYNC FIFO MEM 8KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4255-10AXCT

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 8ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Configurations
Functional Description
The CY7C4255/65 provides five status pins. These pins are decod-
ed to determine one of five states: Empty, Almost Empty, Half Full,
Almost Full, and Full. The Half Full flag shares the WXO pin. This flag
is valid in the stand-alone and width-expansion configurations. In
the depth expansion, this pin provides the expansion out
(WXO) information that is used to signal the next FIFO
when it will be activated.
Selection Guide
Document #: 38-06004 Rev. *A
GND
V
D
D
D
D
D
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
D
CC
D
D
D
D
D
D
D
D
D
14
13
12
11
10
9
5
1
8
7
6
4
3
2
0
Package
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Density
2728 2930
9 8 7
CC1
) (mA)
6
3132 33 34 35 36 37 38 3940 4142 43
5
CY7C4255
CY7C4265
4
3 2 1 68
PLCC, TQFP,
Top View
CY7C4255
PLCC
8K x 18
STQFP
Commercial
Industrial
64-pin
(continued)
67
66 65 64 63 62 61
7C4255/65-10
PLCC, TQFP,
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CY7C4265
16K x18
STQFP
64-pin
100
0.5
V
Q
Q
GND
Q
Q
V
Q
Q
GND
Q
Q
V
Q
Q
GND
Q
10
45
50
4255–2
8
3
8
CC
CC
CC
14
13
12
11
10
9
8
7
6
5
4
/SMODE
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
15
14
13
12
11
10
9
5
1
8
7
6
4
3
2
0
The Empty and Full flags are synchronous, i.e., they change
state relative to either the Read Clock (RCLK) or the Write
Clock (WCLK). When entering or exiting the Empty states, the
flag is updated exclusively by the RCLK. The flag denoting Full
states is updated exclusively by WCLK. The synchronous flag
architecture guarantees that the flags will remain valid from
one clock cycle to the next. The Almost Empty/Almost Full
flags become synchronous if the V
All configurations are fabricated using an advanced 0.5
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
7C4255/65-15
66.7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
10
15
10
45
50
4
1
CY7C4255
CY7C4265
Top View
TQFP/STQFP
7C4255/65-25
40
15
25
15
45
50
6
1
CC
/SMODE is tied to V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
7C4255/65-35
CY7C4255
CY7C4265
Page 2 of 22
28.6
4255–3
20
35
20
45
50
7
2
Q
Q
GND
Q
Q
V
Q
Q
GND
Q
Q
Q
Q
GND
Q
V
CC
CC
14
13
12
11
10
9
8
7
6
5
4
SS
.