CY7C4255-15AXC Cypress Semiconductor Corp, CY7C4255-15AXC Datasheet - Page 15

• Manufacturer Part Number: CY7C4255-15AXC
• Description: IC SYNC FIFO MEM 8KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4255-15AXC

• Function: Synchronous
• Memory Size: 144K (8K x 18)
• Data Rate: 100MHz
• Access Time: 10ns
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Configuration: Dual
• Density: 144Kb
• Access Time (max): 10ns
• Word Size: 18b
• Organization: 8Kx18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 45mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Architecture
The CY7C4256/65 consists of an array of 8K/16K words of 18
bits each (implemented by a dual-port array of SRAM cells), a
read pointer, a write pointer, control signals (RCLK, WCLK, REN,
WEN, RS), and flags (EF, PAE, HF, PAF, FF). The
CY7C4255/65/65A also includes the control signals WXI, RXI,
WXO, RXO for depth expansion.
Resetting the FIFO
Upon power up, the FIFO must be reset with a Reset (RS) cycle.
This causes the FIFO to enter the Empty condition signified by
EF being LOW. All data outputs go LOW after the falling edge of
RS only if OE is asserted. For the FIFO to reset to its default
state, a falling edge must occur on RS and the user must not read
or write while RS is LOW.
FIFO Operation
When the WEN signal is active (LOW), data present on the D
pins is written into the FIFO on each rising edge of the WCLK
signal. Similarly, when the REN signal is active LOW, data in the
FIFO memory are presented on the Q
presented on each rising edge of RCLK while REN is active LOW
and OE is LOW. REN must set up t
a valid read function. WEN must occur tENS before WCLK for it
to be a valid write function.
An output enable (OE) pin is provided to three-state the Q
outputs when OE is deasserted. When OE is enabled (LOW),
data in the output register is available to the Q
t
on the FIFO that is read enabled.
The FIFO contains overflow circuitry to disallow additional writes
when the FIFO is full, and under flow circuitry to disallow
additional reads when the FIFO is empty. An empty FIFO
maintains the data of the last valid read on its Q
after additional reads occur.
Programming
The CY7C4255/65/65A devices contain two 14-bit offset
registers. Data present on D
mines the distance from Empty (Full) that the Almost Empty
(Almost Full) flags become active. If the user elects not to
program the FIFO’s flags, the default offset values are used (see
Table
LOW, data on the inputs D
register on the first LOW-to-HIGH transition of the Write Clock
(WCLK). When the LD pin and WEN are held LOW then data is
written into the Full offset register on the second LOW-to-HIGH
transition of the Write Clock (WCLK). The third transition of the
Write Clock (WCLK) again writes to the Empty offset register
(see
at one time. One or two offset registers can be written and then,
by bringing the LD pin HIGH, the FIFO is returned to normal
Document #: 38-06004 Rev. *E
OE
Note
37. The same selection sequence applies to reading from the registers. REN is enabled and read is performed on the LOW-to-HIGH transition of RCLK.
. If devices are cascaded, the OE function only outputs data
Table
4). When the Load LD pin is set LOW and WEN is set
4). Writing all offset registers does not have to occur
0–13
0–13
is written into the Empty offset
during a program write deter-
ENS
0–17
before RCLK for it to be
outputs. New data is
0–17
0–17
outputs after
outputs even
0–17
0–17
read/write operation. When the LD pin is set LOW, and WEN is
LOW, the next offset register in sequence is written.
The contents of the offset registers can be read on the output
lines when the LD pin is set LOW and REN is set LOW; then,
data can be read on the LOW-to-HIGH transition of the Read
Clock (RCLK).
Table 4. Write Offset Register
Flag Operation
The CY7C4255/65/65A devices provide five flag pins to indicate
the condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if V
tied to V
Full Flag
The Full Flag (FF) goes LOW when device is Full. Write opera-
tions are inhibited whenever FF is LOW regardless of the state
of WEN. FF is synchronized to WCLK: it is exclusively updated
by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) goes LOW when the device is empty. Read
operations are inhibited whenever EF is LOW, regardless of the
state of REN. EF is synchronized to RCLK, i.e., it is exclusively
updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C4255/65/65A features programmable Almost Empty
and Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE are asserted, signifying that
the FIFO is either Almost Full or Almost Empty. See
page 16 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal transition
is caused by the rising edge of the write clock and the PAE flag
transition is caused by the rising edge of the read clock.
LD
0
0
1
1
CY7C4255, CY7C4265, CY7C4265A
WEN
SS
0
1
0
1
.
WCLK
[37]
Writing to offset registers:
Empty Offset
Full Offset
No Operation
Write Into FIFO
No Operation
Selection
Page 15 of 23
CC
/SMODE is
Table 5
on
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