ST62T35B ST Microelectronics, ST62T35B Datasheet - Page 46

• Manufacturer Part Number: ST62T35B
• Description: (ST62E35B / ST62T35B) 8-BIT OTP/EPROM MCUs
• Manufacturer: ST Microelectronics

45
ST62T35B/E35B
4.3.3 TIMINGS MEASUREMENT MODES
These modes are based on the capture of the
down counter content into either CP or RLCP reg-
isters. Some are used in conjunction with a syn-
chronisation of the down counter by reload func-
tions on external event on CPi pins or software
RUNRES setting, while other modes do not affect
the downcounting. As long as RELOAD bit is
cleared, the down counter remains in free running
mode.
4.3.3.1 Timing measurement with startup
control
Three startup conditions, selected by RLDSELi bit
can reload the counter from RLCP and initiate the
down counting when RELOAD bit is set. The first
mode is software controlled through the RUNRES
bit, while the two others are based on external event
on pins CP1 and CP2 with configurable polarities.
External event on CP2 pin (with configurable po-
larities) is used as strobe to launch the capture of
the CT counter into CP. When RELOAD bit is set,
RLCP cannot be used for capture, since it con-
tains the reload value..
Finally, 3 different Reload/Capture sequences are
available:
Figure 26. . CP1 Triggered Restart Mode with CP2 Event Detection
46/82
RELOAD
COUNTER
RUNRES
1
0
CP2
CP1
CT
Disabled
Disabled
Reload on CP1,CP2, RUNRES / Capture CP2
Capture CP1 / Capture CP2
Enable the Inputs
0000h
Reload and Start
Set CP1FLG
Capture CT into CP
Set CP2FLG
Set CP1ERR
Reload
Set CP2ERR
Clear all Flags
– CP1 triggered restart mode with CP2 event de-
– CP2 triggered restart mode with second CP2
– Software triggered restart mode with CP2 event
CP1 triggered restart mode with CP2 event de-
tection.
This mode is enabled for RLDSEL2=0 and
RLDSEL1=1.
External events on CPi pins are enabled as soon as
RUNRES bit is set, which lets the prescaler and the
down counter running. The next active edge on CP1
causes the counter to be loaded from RLCP, the
CP1FLG to be set and the downcounting startsfrom
RLCP value. Each following active edge on CP1 will
cause a reload of the counter. If CP1FLG is not re-
set before the next reload, the CP1ERR flag is set
at the same time as the counter is reloaded. Both
flags should then be cleared by software.
While the counter is counting, any active edge on
CP2 will capture the value of the counter at that in-
stant into the CP Register and set the CP2FLG bit.
If CP2FLG is not cleared before the following CP2
event, the CP2ERR flag bit is set, and no new cap-
ture can be performed
Capturing is re-enabled by clearing both CP2FLG
and CP2ERR.
If a capture on CP2 and a reload on CP1 occur at the
same time, the capture of the counter to CP is made
first, and then the counter is reloaded from RLCP.
tection.
event detection.
detection.
Set CP1FLG
Reload
Set CP1ERR, CP2FLG
First Capture in CP
Then Reload
Software Reset
Disabled
Disabled
VR02007
0000h