AD9520-0 Analog Devices, Inc., AD9520-0 Datasheet - Page 11

• Manufacturer Part Number: AD9520-0
• Description: 12 Lvpecl/24 Cmos Output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVPECL ABSOLUTE PHASE NOISE
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVPECL OUTPUT ABSOLUTE TIME JITTER
VCO = 2.95 GHz; Output = 2.95 GHz
VCO = 2.75 GHz; Output = 2.75 GHz
VCO = 2.55 GHz; Output = 2.55 GHz
VCO = 2.949 GHz; LVPECL = 245.76 MHz; PLL LBW = 63 kHz
VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 63 kHz
VCO = 2.703 GHz; LVPECL = 61.44 MHz; PLL LBW = 63 kHz
VCO = 2.799 GHz; LVPECL = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 2.703 GHz; LVPECL = 122.88 MHz; PLL LBW = 2.1 kHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
Typ
−46
−78
−104
−123
−139
−145
−49
−80
−106
−125
−140
−146
−51
−82
−108
−127
−140
−146
Rev. 0 | Page 11 of 84
Min
Min
Max
Typ
652
607
176
158
177
Typ
351
324
330
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Max
Max
Unit
fs rms
fs rms
Test Conditions/Comments
Internal VCO; direct-to-LVPECL output and for loop
bandwidths < 1 kHz
fs rms
fs rms
fs rms
Unit
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
jittery, so a narrower PLL loop bandwidth
is used; reference = 19.44 MHz; R DIV = 162
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R DIV = 1
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
AD9520-0