AD9049 Analog Devices, Inc., AD9049 Datasheet - Page 8

• Manufacturer Part Number: AD9049
• Description: 9-bit, 30 Msps Adc
• Manufacturer: Analog Devices, Inc.

AD9049
THEORY OF OPERATION
Refer to the block diagram on the front page.
The AD9049 employs a subranging architecture with digital
error correction. This combination of design techniques ensures
true 9-bit accuracy at the digital outputs of the converter.
At the input, the analog signal is buffered by a high speed differ-
ential buffer and applied to a track-and-hold (T/H) that holds
the analog value which is present when the unit is strobed with
an ENCODE command. The conversion process begins on the
rising edge of this pulse. The two stage architecture completes a
coarse and then a fine conversion of the T/H output signal.
Error correction and decode logic correct and align data from
the two conversions and present the result as a 9-bit parallel
digital word. Output data are strobed on the rising edge of the
ENCODE command. The subranging architecture results in
five pipeline delays for the output data. Refer to the AD9049
Timing Diagram.
USING THE AD9049
3 V System
The digital input and outputs of the AD9049 can easily be
configured to directly interface to 3 V logic systems. The encode
input (Pin 13) is TTL compatible with a logic threshold of 1.5
V. This input is actually a CMOS stage (refer to Equivalent En-
code Input Stage) with a TTL threshold, allowing operation
with TTL, CMOS and 3 V CMOS logic families. Using 3 V
CMOS logic allows the user to drive the encode directly without
the need to translate to +5 V. This saves the user power and
board space. As with all high speed data converters, the clock
signal must be clean and jitter free to prevent the degradation of
dynamic performance.
The AD9049 outputs can also directly interface to 3 V logic
systems. The digital outputs are standard CMOS stages (refer to
AD9049 Output Stage) with isolated supply pins (Pins 20, 22
V
levels vary respectively. By connecting Pins 20 and 22 to the
3 V logic supply, the AD9049 will supply 3 V output levels.
Care should be taken to filter and isolate the output supply of
the AD9049 as noise could be coupled into the ADC, limiting
performance.
Analog Input
The analog input of the AD9049 is a differential input buffer
(refer to AD9049 Equivalent Analog Input). The differential in-
puts are internally biased at +3.3 V, obviating the need for
external biasing. Excellent performance is achieved whether the
analog inputs are driven single-ended or differential. (For best
dynamic performance, impedances at AIN and AINB should
match.)
Figure 16 shows typical connections for the analog inputs when
using the AD9049 in a dc coupled system with single ended
signals. All components are powered from a single +5 V supply.
The AD820 is used to offset the ground referenced input signal
to the level required by the AD9049.
AC coupling of the analog inputs to the AD9049 is easily accom-
plished. Figure 17 shows capacitive coupling of a single ended
signal while Figure 18 shows transformer coupling differentially
into the AD9049.
DD
). By varying the voltage on the V
DD
pins, the digital output
–8–
The AD830 provides a unique method of providing dc level shift
for the analog input. Using the AD830 allows a great deal of
flexibility for adjusting offset and gain. Figure 19 shows the
AD830 configured to drive the AD9049. The offset is provided
by the internal biasing of the AD9049 differential input (Pin 9).
For more information regarding the AD830, see the AD830
data sheet.
Figure 17. Single Ended, Capacitively Coupled AD9049
Figure 16. Single Supply, Single Ended, DC Coupled
AD9049
Figure 18. Differentially Driven AD9049 Using Trans-
former Coupling.
–0.5V to +0.5V
–0.5V to +0.5V
–0.5V to +0.5V
–0.5V to +0.5V
V
Figure 19. Level Shifting with the AD830
IN
V
V
V
IN
IN
IN
1k
0.1µF
1k
1k
1k
2
3
1
4
AD830
1k
+5V
–5V
1k
+15V
–5V
1k
+5V
–5V
1k
+5V
AD8011
AD820
AD8011
AD8041
7
0.1µF
+5V
50
0.1 F
0.1µF
0.1µF
9
10
T1-1T
10
10
9
9
0.1µF
AD9049
10
9
AD9049
AD9049
+5V
AD9049
+5V
+5V
+5V
REV. A