AD9721 Analog Devices, Inc., AD9721 Datasheet - Page 3

• Manufacturer Part Number: AD9721
• Description: Ad9731 10-bit, 170 Msps
• Manufacturer: Analog Devices, Inc.

SPECIFICATIONS
REV. B
Parameter
SFDR PERFORMANCE (Narrowband)
INTERMODULATION DISTORTION
POWER SUPPLY
NOTES
10
11
12
13
14
15
Specifications subject to change without notice.
1
2
3
4
5
6
7
8
9
Measured with R
Data must remain stable for specified time prior to rising edge of CLOCK.
Data must remain stable for specified time after rising edge of CLOCK.
SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst-case spurious frequencies in the output spectrum window.
The frequency span is dc-to-Nyquist unless otherwise noted.
Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at (2F
Supply voltages should remain stable within ± 5% for nominal operation.
Measured as an error in ratio of full-scale current to current through R
Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification.
Internal reference output current defines load conditions applied during Internal Reference Voltage test.
Full-scale current variations among devices are higher when driving REFERENCE IN directly.
Frequency at which a 3 dB change in output of DAC is observed; R
Based on I
Measured as voltage settling at midscale transition to ± 0.5 LSB, R
Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
Peak glitch impulse is measured as the largest area under a single positive or negative transient.
2 MHz; 2 MHz Span
25 MHz, 2 MHz Span
10 MHz, 5 MHz Span (Clock = 170 MHz)
F1 = 800 kHz, F2 = 900 kHz
Digital –V Supply Current
Analog –V Supply Current
Digital +V Supply Current
Power Dissipation
PSRR
FS
ANALOG OUTPUT
= 32 (CONTROL AMP IN/R
L
= 50 W and DAC operating in latched mode.
ANALOG OUTPUT
15
CLOCK
DATA
CLOCK
DETAIL OF SETTLING TIME
2
–F
CODE 1
1
DATA
) and (2F
SET
CODE 1
t
PD
) when using internal control amplifier. DAC load is virtual ground.
t
S
13
14
1
–F
t
2
ST
) of the two tones.
ERROR BAND
pw
SPECIFIED
Figure 1. Timing Diagrams
Temp
25∞C
25∞C
25∞C
25∞C
25∞C
Full
25∞C
Full
25∞C
Full
25∞C
Full
25∞C
MIN
CODE 2
DATA
L
CODE 2
L
= 50 W.
t
= 50 W; 100 mV modulation at midscale.
H
SET
(640 mA nominal); ratio is nominally 32. DAC load is virtual ground.
pw
MAX
–3–
Test
Level
V
V
V
V
I
VI
I
VI
I
VI
V
V
V
CODE 3
DATA
CODE 3
Min
H
GLITCH AREA =
1/2 HEIGHT
W
CODE 4
CODE 4
Typ
79
61
73
58
27
27
45
45
13
15
439
449
100
WIDTH
DATA
Max
37
42
53
66
20
22
AD9731
Unit
dB
dB
dB
dB
mA
mA
mA
mA
mA
mA
mW
mW
mA/V