AD9522 Analog Devices, Inc., AD9522 Datasheet - Page 10

• Manufacturer Part Number: AD9522
• Description: 12 Lvds/24 Cmos Output Clock Generator With Integrated 2.8 Ghz Vco
• Manufacturer: Analog Devices, Inc.

AD9522-0
CLOCK OUTPUT ABSOLUTE PHASE NOISE (INTERNAL VCO USED)
Table 7.
Parameter
LVDS ABSOLUTE PHASE NOISE
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO)
Table 8.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO)
Table 9.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
VCO = 2950 MHz; Output = 737.5 MHz
VCO = 2750 MHz; Output = 685 MHz
VCO = 2550 MHz; Output = 632.5 MHz
VCO = 2949 MHz; LVDS = 245.76 MHz; PLL LBW = 55 kHz
VCO = 2580 MHz; LVDS = 122.88 MHz; PLL LBW = 55 kHz
VCO = 2580 MHz; LVDS = 61.44 MHz; PLL LBW = 55 kHz
VCO = 2799 MHz; LVDS = 155.52 MHz; PLL LBW = 1.8 kHz
VCO = 2580 MHz; LVDS = 122.88 MHz; PLL LBW = 1.8 kHz
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 40 MHz Offset
Min
Typ
−59
−90
−115
−133
−146
−149
−60
−92
−118
−135
−148
−151
−64
−95
−120
−137
−148
−151
Rev. 0 | Page 10 of 84
Min
Max
Min
Typ
617
514
218
Typ
187
352
166
321
378
Unit
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Max
Max
Test Conditions/Comments
Internal VCO; VCO divider = 4; LVDS output and
for loop bandwidths < 1 kHz
Unit
fs rms
fs rms
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Application example based on a typical
setup where the reference source is jittery,
so a narrower PLL loop bandwidth is used;
reference = 19.44 MHz; R DIV = 162
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 200 kHz to 10 MHz
Test Conditions/Comments
Application example based on a typical
setup where the reference source is
clean, so a wider PLL loop bandwidth is
used; reference = 15.36 MHz; R DIV = 1
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 12 kHz to 20 MHz