AD9522-2 Analog Devices, Inc., AD9522-2 Datasheet - Page 11
![no-image](/images/no-image-200.jpg)
AD9522-2
Manufacturer Part Number
AD9522-2
Description
12 Lvds/24 Cmos Output Clock Generator With Integrated 2.2 Ghz Vco
Manufacturer
Analog Devices, Inc.
Datasheet
1.AD9522-2.pdf
(84 pages)
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CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING EXTERNAL VCXO)
Table 10.
Parameter
LVDS OUTPUT ABSOLUTE TIME JITTER
CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER NOT USED)
Table 11.
Parameter
LVDS OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
LVDS = 245.76 MHz; PLL LBW = 125 Hz
LVDS = 122.88 MHz; PLL LBW = 125 Hz
LVDS = 61.44 MHz; PLL LBW = 125 Hz
CLK = 622.08 MHz
CLK = 622.08 MHz
CLK = 100 MHz
CLK = 500 MHz
CLK = 200 MHz
Any LVDS Output = 622.08 MHz
Divide Ratio = 1
Any LVDS Output = 155.52 MHz
Divide Ratio = 4
Any LVDS Output = 100 MHz
Divide Ratio = 1
Any LVDS Output = 100 MHz
Divide Ratio = 5
Any CMOS Output Pair = 100 MHz
Divide Ratio = 2
Min
Min
Typ
87
108
146
120
151
207
157
210
295
Typ
69
116
263
242
289
Rev. 0 | Page 11 of 84
Max
Max
Unit
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Unit
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Test Conditions/Comments
Application example based on a typical setup using an
external 245.76 MHz VCXO (Toyocom TCO-2112);
reference = 15.36 MHz; R DIV = 1
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Integration BW = 200 kHz to 5 MHz
Integration BW = 200 kHz to 10 MHz
Integration BW = 12 kHz to 20 MHz
Test Conditions/Comments
Distribution section only; does not include
PLL and VCO; measured at rising edge of
clock signal
Integration bandwidth = 12 kHz to 20 MHz
Integration bandwidth = 12 kHz to 20 MHz
Calculated from SNR of ADC method
Broadband jitter
Calculated from SNR of ADC method
Broadband jitter
Distribution section only; does not include
PLL and VCO
Calculated from SNR of ADC method
Broadband jitter
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