AD9248BST-65 Analog Devices, Inc., AD9248BST-65 Datasheet

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AD9248BST-65

Manufacturer Part Number
AD9248BST-65
Description
14-bit, 20/40/65 Msps Dual A/ D Converter
Manufacturer
Analog Devices, Inc.
Datasheet

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FEATURES
Integrated Dual 14-Bit A-to-D Converters
Single 3 V Supply Operation (2.7 V to 3.6 V)
SNR = 73 dBc (to Nyquist, AD9248-65)
SFDR = 83 dBc (to Nyquist, AD9248-65)
Low Power: 600 mW at 65 MSPS
Differential Input with 500 MHz 3 dB Bandwidth
Exceptional Cross Talk Immunity > 85dB
Flexible Analog Input: 1 V p-p to 2 V p-p Range
Offset Binary or Twos Complement Data Format
Clock Duty Cycle Stabilizer
APPLICATIONS
Ultrasound Equipment
IF Sampling in Communications Receivers:
IS-95, CDMA One, IMT-2000
Battery-Powered Instruments
Hand-Held Scopemeters
Low Cost Digital Oscilloscopes
GENERAL DESCRIPTION
The AD9248 is a dual, 3 V, 14-bit, 20/40/65 MSPS analog-to-
digital converter. It features dual high performance sample-and
hold amplifiers and an integrated voltage reference. The
AD9248 uses a multistage differential pipelined architecture
with output error correction logic to provide 14-bit accuracy
and guarantee no missing codes over the full operating
temperature range at up to 65 MSPS data rates. The wide
bandwidth, differential SHA allows for a variety of user
selectable input ranges and offsets including single-ended
applications. It is suitable for various applications including
multiplexed systems that switch full-scale voltage levels in
successive channels and for sampling inputs at frequencies well
beyond the Nyquist rate.
Dual single-ended clock inputs are used to control all internal
conversion cycles. A duty cycle stabilizer is available on the
AD9248-65 and can compensate for wide variations in the
clock duty cycle, allowing the converters to maintain excellent
performance. The digital output data is presented in either
straight binary or twos complement format. Out-of-range
signals indicate an overflow condition, which can be used with
the most significant bit to determine low or high overflow.
Fabricated on an advanced CMOS process, the AD9248 is
available in a space saving 64-lead LQFP and is specified over
the industrial temperature range (–40? C to +85? C).
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
Preliminary Technical Data
6/29/2004
PRODUCT HIGHLIGHTS
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
14-Bit, 20/40/65 MSPS
1.
2.
3.
4.
5.
6.
7.
8.
REFB_A
REFT_A
REFT_B
REFB_B
VIN+_A
VIN- _A
SENSE
VIN+_B
AGND
VIN-_B
VREF
Dual A/ D Converter
Pin compatible with AD9238, 12-bit 20/40/65MSPS
ADC.
Speed grade options of 20 MSPS, 40 MSPS, and 65
MSPS allow flexibility between power, cost, and
performance to suit an application.
Low power consumption:
AD9248-65: 65 MSPS = 600 mW.
AD9248-40: 40 MSPS = 330 mW.
AD9248-20: 20 MSPS = 180 mW.
The patented SHA input maintains excellent
performance for input frequencies up to 100 MHz and
can be configured for single-ended or differential
operation.
Typical channel isolation of 85 dB @ f
The clock duty cycle stabilizer (AD9248-65 only)
maintains performance over a wide range of clock
duty cycles.
The OTR output bits indicate when either input signal
is beyond the selected input range.
Multiplexed data output option enables single-port
operation from either data port A or data port B.
AD9248
Figure 1. Functional Block Diagram
+
-
0.5V
SHA
SHA
DRVDD
AVDD
ADC
ADC
DRGND
AGND
14
14
Duty Cycle
Stabilizer
AD9248
Control
Clock
Mode
www.analog.com
14
14
IN
= 10 MHz.
OTR_B
OTR_A
OEB_B
D13
OEB_A
MUX_SELECT
CLK_A
CLK_B
DCS
SHARED_REF
PWDN_A
PWDN_B
DFS
D13
A
B
-D
-D
0A
0B

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AD9248BST-65 Summary of contents

Page 1

... Multiplexed data output option enables single-port operation from either data port A or data port B. 6/29/2004 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9248 AGND AVDD OTR_A 14 D13 -D ...

Page 2

AD9248 TABLE OF CONTENTS General Description .............................................................. 1 Product Highlights ................................................................ 1 DC Specifications (Continued) ............................................. 5 Switching Specifications ....................................................... 6 AC Specifications ................................................................. 7 Absolute Maximum Ratings ..................................................... 9 ESD Caution ......................................................................... 9 Terminolgy .......................................................................... 12 Typical Performance CharacteristiC ...

Page 3

... 2.7 3.0 3.6 2.7 IV 2.25 3.0 3.6 2. ±0.01 V 180 VI 190 212 V 2.0 Rev. PrE | Page AD9248 AD9248BST/BCP Typ Max Min Typ Max 14 14 ±0.5 ±0.5 ±0.7 ±0.7 ±0.5 ±0.5 ±0.5 ±0.5 ±1.4 ±1.4 ±1.4 ±1.4 ±10 ±10 ±12 ±12 ±5 ±35 ±5 ± ...

Page 4

AD9248 CHARACTERISTICS Offset Error Full Gain Error Full 1 Gain error and gain temperature coefficient are based on the A/D converter only (with a fixed 1.0 V external reference). 2 Measured at maximum clock rate with a low frequency sine ...

Page 5

... AD9248BST/BCP- AD9248BST/BCP- 20 Level Min Typ Max Min IV 2.0 2 3.29 3.29 IV 3.25 3.25 IV 0.05 IV 0.2 IV 2.49 2.49 IV 2.45 2.45 IV 0.05 IV 0.2 Rev. PrE | Page AD9248 AD9248BST/BCP Typ Max Min Typ Max 2.0 0.8 0.8 + + 3.29 3.25 0.05 0.05 0.2 0.2 2.49 2.45 0.05 0.05 0.2 0.2 Unit V V µA µ ...

Page 6

... Min Typ Max Full VI 20 Full V 1 Full V 50.0 Full V 15.0 Full V 15.0 Full VI 2 3.5 6 Full V 7 Full V 1.0 Full V 0.5 Full V 2.5 Full V 2 Rev. PrE | Page AD9248BST/BCP- AD9248BST/BCP Min Typ Max Min Typ 25.0 15.4 8.8 6.2 8.8 6 1.0 1.0 0.5 0.5 2.5 2 Max Unit MSPS 1 MSPS ...

Page 7

... IV 25°C V 11.4 25° 83.0 Full V - 81.0 25° 83.0 tbd Full V 25°C I Full V 25°C I 25° 77.0 Full V - 84.0 Full V Full V Rev. PrE | Page AD9248 AD9248BST/BCP- AD9248BST/BCP Min Typ Max Min Typ tbd 72 72 tbd 72.8 72.6 71.9 tbd 71.6 71.5 tbd 71 69.5 69.4 11.8 11.8 11.7 tbd 11.7 11.6 tbd 11 ...

Page 8

AD9248 f = 2.4 MHz INPUT f = 9.7 MHz INPUT f = 19.6 MHz INPUT f = 32.5 MHz INPUT f = 100 MHz INPUT CROSSTALK Specifications subject to change without notice. Preliminary Technical Data 25°C V 86.0 Full ...

Page 9

Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 5. AD9248 Absolute Maximum Ratings Parameter Pin Name ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs CLK, DCS, MUX_SELECT, SHARED_REF, OEB, DFS VINA, VINB VREF SENSE REFB, REFT PDWN 2 ENVIRONMENTAL Operating Temperature Junction ...

Page 10

AD9248 AGND VIN+_A VIN – _A AGND AVDD REFT_A REFB_A VREF SENSE REFB_B REFT_B AVDD AGND VIN– _B VIN+_B AGND Table 6. Pin Function Descriptions Pin Mnemonic Number 2 VIN+_A 3 VIN–_A 15 VIN+_B 14 VIN REFT_A 7 ...

Page 11

... Lead Frame Chip Scale Package (LFCSP) 64-Lead LOW PROFILE QUAD FLAT PACK (TQFP) 64-Lead LOW PROFILE QUAD FLAT PACK (TQFP) 64-Lead LOW PROFILE QUAD FLAT PACK (TQFP) Evaluation Board with AD9248BST-20 Evaluation Board with AD9248BST-40 Evaluation Board with AD9248BST-65 Rev. PrE | Page AD9248 Package Option CP-64-1 CP-64-1 ...

Page 12

AD9248 TERMINOLGY Aperture Delay Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. Aperture Jitter The variation in ...

Page 13

Preliminary Technical Data Crosstalk Coupling onto one channel being driven 0.5 dBFS) signal when the adjacent interfering channel is driven by a full- scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components. ...

Page 14

AD9248 TYPICAL PERFORMANCE CHARACTERISTIC Preliminary Technical Data Rev. PrE | Page ...

Page 15

Preliminary Technical Data EQUIVALENT CIRCUITS Equivalent Analog Input Circuit Figure xx. THEORY OF OPERATION The AD9248 consists of two high performance analog-to- digital converters (ADCs) that are based on the AD9235 converter core. The dual ADC paths are independent, except ...

Page 16

AD9248 input; therefore, the precise values are dependant on the application under sampling applications, any shunt capacitors should be removed. In combination with the driving source impedance, they would limit the input bandwidth. For best dynamic performance, the ...

Page 17

Preliminary Technical Data degradation in SFDR and in distortion performance due to the large input common- mode swing. However, if the source impedances on each input are matched, there should be little effect on SNR performance. CLOCK INPUT AND CONSIDERATIONS ...

Page 18

AD9248 The data format can be selected for either offset binary or twos complement. This is discussed later in the Data Format section. TIMING The AD9248 provides latched data outputs with a pipeline delay of seven clock cycles. Data outputs ...

Page 19

Preliminary Technical Data VOLTAGE REFERENCE A stable and accurate 0.5 V voltage reference is built into the AD9248. The input range can be adjusted by varying the reference voltage applied to the AD9248, using either the internal reference with different ...

Page 20

AD9248 AD9248 Figure xx. Programmable Reference Configuration Typical V Figure xx. REF Preliminary Technical Data Drift Rev. PrE | Page Accuracy vs. Load Figure xx. REF ...

Page 21

Preliminary Technical Data EVALUATION BOARD DIAGRAMS Rev. PrE | Page AD9248 ...

Page 22

AD9248 OUTLINE DIMENSIONS Figure 5. Preliminary Technical Data 64-Lead Lead Frame Chip Scale Package (LFCSP) Rev. PrE | Page ...

Page 23

Preliminary Technical Data Rev. PrE | Page AD9248 ...

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