22C10 CatalystSemiconductor, 22C10 Datasheet - Page 8

• Manufacturer Part Number: 22C10
• Description: 256-BitNonvolatileCMOSStaticRAM
• Manufacturer: CatalystSemiconductor

Figure 4. Recall Cycle Timing
Figure 5. Store Cycle Timing
Doc. No. 25018-0A 2/98 N-1
Recall
At anytime, except during a store operation, taking the
RECALL pin low will initiate a recall operation. This is
independent of the state of CS, WE, or A
RECALL pin has been held low for the duration of the
Recall Pulse Width (t
pendent of any other inputs. During the recall, the entire
contents of the E
RAM array. The first byte of data may be externally
accessed after the recalled data access time from end of
recall (t
accessed by using the normal read mode.
If the RECALL pin is held low for the entire Recall Cycle
time (t
immediately accessed by using the normal read mode.
A recall operation can be performed an unlimited num-
ber of times without affecting the integrity of the data.
The outputs I/O
state as long as the RECALL signal is held low.
Store
At any time, except during a recall operation, taking the
STORE pin low will initiate a store operation. This takes
ADDRESS
DATA I/O
DATA I/O
RCC
RECALL
ARC
STORE
), the contents of the Static RAM may be
) is met. After this, any other byte may be
CS
0
2
–I/O
PROM array is transferred to the Static
RCP
3
will go into the high impedance
), the recall will continue inde-
t RCZ
t STZ
t STP
t RCP
0
–A
5
. After the
HIGH-Z
t STC
HIGH-Z
8
t RCC
place independent of the state of CS, WE or A
STORE pin must be held low for the duration of the Store
Pulse Width (t
initiated. Once initiated, the STORE pin becomes a
“Don’t Care”, and the store operation will complete its
transfer of the entire contents of the Static RAM array
into the E
(t
the contents of the addressed Static RAM byte and its
corresponding byte in the E
known.
During the store operation, the outputs are in a high
impedance state. A minimum of 100,000 store opera-
tions can be performed reliably and the data written into
the E
of 10 years.
DATA PROTECTION DURING POWER-UP AND
POWER-DOWN
The CAT22C10 has on-chip circuitry which will prevent
a store operation from occurring when V
3.0V typ. This function eliminates the potential hazard of
spurious signals initiating a store operation when the
system power is below 3.0V typ.
STC
). If a store operation is initiated during a write cycle,
2
PROM array has a minimum data retention time
t ORC
DATA UNDEFINED
t ARC
2
PROM array within the Store Cycle time
STP
) to ensure that a store operation is
2
DATA VALID
PROM array will be un-
t OST
CC
falls below
0
–A
5153 FHD F08
5153 FHD F07
5
. The