74HCT112D,652 NXP Semiconductors, 74HCT112D,652 Datasheet - Page 2

• Manufacturer Part Number: 74HCT112D,652
• Description: IC FLIP FLOP DUAL JK NEG 16SOIC
• Manufacturer: NXP Semiconductors
• Series: 74HCTr
• Type: JK Typer

Specifications of 74HCT112D,652

• Package / Case: 16-SOIC (3.9mm Width)
• Function: Set(Preset) and Reset
• Output Type: Differential
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Frequency - Clock: 64MHz
• Trigger Type: Negative Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: 74HCT
• Logic Type: Dual JK Flip-Flop
• Polarity: Inverting/Non-Inverting
• Input Type: Single-Ended
• Propagation Delay Time: 19 ns
• High Level Output Current: - 6 mA
• Supply Voltage (max): 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Supply Voltage (min): 4.5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Delay Time - Propagation: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1506-5; 74HCT112D; 933714970652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nS
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
1998 Jun 10
SYMBOL
t
f
C
C
PHL
max
Asynchronous set and reset
Output capability: standard
I
I
PD
Dual JK flip-flop with set and reset;
negative-edge trigger
CC
f
f
C
V
For HCT the condition is V
i
o
/ t
CC
PD
L
category: flip-flops
= input frequency in MHz
= output frequency in MHz
(C
PLH
D
P
) and reset (nR
= output load capacitance in pF
L
= supply voltage in V
is used to determine the dynamic power dissipation (P
D
= C
V
CC
amb
PD
2
PARAMETER
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per flip-flop notes 1 and 2
= 25 C; t
nCP to nQ, nQ
nS
nR
V
f
o
CC
) = sum of outputs
D
D
to nQ, nQ
2
to nQ, nQ
D
) inputs.
f
r
i
= t
I
= GND to V
I
f
= GND to V
= 6 ns
(C
L
V
CC
2
CC
CC
f
o
) where:
1.5 V
2
CONDITIONS
C
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
L
D
= 15 pF; V
in W):
CC
= 5 V
17
15
18
66
3.5
27
HC
TYPICAL
74HC/HCT112
Product specification
19
15
19
70
3.5
30
HCT
ns
ns
ns
MHz
pF
pF
UNIT