AD5273 Analog Devices, AD5273 Datasheet - Page 16

• Manufacturer Part Number: AD5273
• Description: 64-Position OTP Digital Potentiometer
• Manufacturer: Analog Devices

www.DataSheet4U.com
FET N
(V
100 mA with a 5 V supply. For precision applications, a voltage
reference such as ADR421, ADR03, or ADR370 can be applied
at the A terminal of the digital potentiometer.
Programmable Current Source
A programmable current source can be implemented with the
circuit shown in Figure 15. The load current is simply the voltage
across terminals B-to-W of the AD5273 divided by R
at zero-scale, the A terminal of the AD5273 will be at –2.048 V,
which makes the wiper voltage clamped at ground potential.
Dependent on the load, Equation 5 is therefore valid only at cer-
tain codes. For example, when the compliance voltage V
half of the V
to full-scale of the AD5273.
Gain Control Compensation
As seen in Figure 16, the digital potentiometers are commonly
used in gain controls or sensor transimpedance amplifi er signal
conditioning applications.
In both applications, one of the digital potentiometer terminals is
connected to the op amp inverting node with fi nite terminal capaci-
tance C1. It introduces a zero for the 1
whereas a typical op amp GBP has –20 dB/dec characteristics. A
large R2 and fi nite C1 can cause this zero’s frequency to fall well
below the crossover frequency. Thus the rate of closure becomes
40 dB/dec and the system has 0° phase margin at the crossover
frequency. The output may ring or in the worst case oscillate when
AD5273
IN
–V
I
L
Figure 16. Typical Noninverting Gain Amplifi er
1
OUT
. N
=
3
Figure 15. Programmable Current Source
(
2
V
)
1
4
V
GND
REF
+5V
REF191
IN
REF
power handling must be adequate to dissipate
–2.048 + V
U1
, the current can be programmed from midscale
I
V
L
OUT
R
¥
power. This circuit can source a maximum of
S
D
L
) / 64
6
47k
C1
R1
C1
0 TO (2.048 + V
32
1 F
AD5273
U2
OP1177
£
V+
V–
U3
V
–5V
I
D
100k
+5V
B
£
L
U1
)
4.7pF
R2 A
C2
63
A
B
W
W
o
term with 20 dB/dec
R
R
V
L
S
O
102
100
V
L
S
. Notice
I
L
L
equals
(5)
–16–
the input is a step function. Similarly, it is also likely to ring when
switching between two gain values because this is equivalent to a
step change at the input. To reduce the effect of C1, users should
also confi gure B or A rather than W terminal at the inverting node.
Depending on the op amp GBP, reducing the feedback resistor may
extend the zero’s frequency far enough to overcome the problem.
A better approach is to include a compensation capacitor C2 to
cancel the effect caused by C1. Optimum compensation occurs
when R1
variation of R2. As a result, one may use the relationship above
and scale C2 as if R2 is at its maximum value. Doing so may
overcompensate by slowing down the settling time when R2 is
set at low values. As a result, C2 should be found empirically for
a given application. In general, C2 in the range of a few pF to no
more than a few tenths of a pF is adequate for the compensation.
There is also a W terminal capacitance connected to the output
(not shown); its effect on stability is less signifi cant so that the
compensation may not be necessary unless the op amp is driving
a large capacitive load.
Programmable Low-Pass Filter
In A/D conversion applications, it is common to include an anti-
aliasing fi lter to band-limit the sampling signal. To minimize various
system redesigns, users may use two 1 k AD5273s to construct a
generic second-order Sallen Key low-pass fi lter. Since the AD5273
is a single supply device, the input must be dc offset when an ac
signal is applied to avoid clipping at ground. This is illustrated in
Figure 17. The design equations are:
Users can fi rst select some convenient values for the capacitors.
To achieve maximally fl at bandwidth where Q = 0.707, let C1 be
twice the size of C2 and let R1 = R2. As a result, R1 and R2 can
be adjusted to the same setting to achieve the desirable bandwidth.
Level Shift for Different Voltages Operation
When users need to interface a 2.5 V controller with the AD5273,
a proper voltage level shift must be employed so that the digital
potentiometer can be read from or written to the controller;
Figure 18 shows one of the implementations. M1 and M2 should
be low threshold N-Ch Power MOSFETs such as FDV301N.
V
Q
w
V
O
O
I
=
=
=
R1C1
S
C1 = R2
V
Figure 17. Sallen Key Low-Pass Filter
2
R1R2C1C2
1
I
+
SAME SETTINGS
w
ADJUSTED TO
+
Q
A
w
1
O
R1
R2C2
O
S
2
W
B
1
+
C2. This is not an option because of the
A
w
R2
O
W C2
2
B
C1
C
C
U1
AD8601
+2.5V
–2.5V
V+
V–
V
O
REV. 0
(6)
(7)
(8)