AD5293 Analog Devices, AD5293 Datasheet - Page 13

• Manufacturer Part Number: AD5293
• Description: Digital Potentiometer
• Manufacturer: Analog Devices

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Preliminary Technical Data
RDAC ARCHITECTURE
In order to achieve optimum cost performance, Analog Devices
has patented the RDAC segmentation architecture for all the
digital potentiometers. In particular, the AD5293 employs a
3-stage segmentation approach as shown in Figure 7. The
AD5293 wiper switch is designed with the transmission gate
CMOS topology and with the gate voltage derived from V
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation - 1% Resistor Tolerance
The AD5293 operates in rheostat mode when only two termi-
nals are used as a variable resistor. The unused terminal can
be floating or tied to the W terminal as shown in Figure 8.
The nominal resistance between Terminal A and Terminal B,
R
points accessed by the wiper terminal. The 10-bit data in the
RDAC latch is decoded to select one of the 1,024 possible wiper
settings. The AD5293 contains an internal ±1% resistor toler-
ance calibration feature which can be disabled or enabled,
enabled by default, by programming bit C2 of the control
register (Table 8). The digitally programmed output resistance
between the W terminal and the A terminal, R
terminal and B terminal, R
AB
, is available in 20 kΩ, 50 kΩ, and 100 kΩ and has 1,024 tap
Figure 7. AD5293 Simplified RDAC Circuit.
Figure 8. Rheostat Mode Configuration
WB
, is calibrated to give a maximum
WA
and the W
DD
Rev. PrA | Page 13 of 15
.
of ±1% absolute resistance error over both the full supply and
temperature ranges. As a result, the general equation for
determining the digitally programmed output resistance
between the W terminal and B terminal is
where:
D is the decimal equivalent of the binary code loaded in
the 10-bit RDAC register.
R
Similar to the mechanical potentiometer, the resistance of
the RDAC between the W terminal and the A terminal also
produces a digitally controlled complementary resistance, R
R
resistance error. R
and decreases as the data loaded into the latch increases. The
general equation for this operation is
D is the decimal equivalent of the binary code loaded in
the 10-bit RDAC register.
R
In the zero-scale condition, a finite total wiper resistance of
TBD Ω is present. Regardless of which setting the part is oper-
ating in, care should be taken to limit the current between
the A terminal to B terminal, W terminal to A terminal, and
W terminal to B terminal, to the maximum continuous current of
±3 mA(20KΩ) or ±2 mA(50KΩ and 100 KΩ) or pulse current of
TBD mA. Otherwise, degradation, or possible destruction of the
internal switch contact, can occur.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider
at wiper to B and wiper to A proportional to the input voltage
at A to B as shown in Figure 9. Unlike the polarity of V
GND, which must be positive, voltage across A to B, W to A,
and W to B can be at either polarity.
If ignoring the effect of the wiper resistance for simplicity, con-
necting the A terminal to 30 V and the B terminal to ground
produces an output voltage at the Wiper W to Terminal B
where:
AB
WA
AB
is the end-to-end resistance.
is the end-to-end resistance.
is also calibrated to give a maximum of 1% absolute
Figure 9. Potentiometer Mode Configuration
R
WA
WA
R
WB
starts at the maximum resistance value
(
D
(
D
)
=
)
=
, 1
, 1
024
, 1
024
D
024
−
×
D
R
×
AB
R
AB
AD5293
DD
(1)
(2)
to
WA
.