AD573 Analog Devices, AD573 Datasheet - Page 6

• Manufacturer Part Number: AD573
• Description: 10-Bit A/D Converter
• Manufacturer: Analog Devices

AD573
CONTROL AND TIMING OF THE AD573
The operation of the AD573 is controlled by three inputs:
CONVERT, HBE and LBE.
Starting a Conversion
The conversion cycle is initiated by a positive going CONVERT
pulse at least 500 ns wide. The rising edge of this pulse resets
the internal logic, clears the result of the previous conversion,
and sets DR high. The falling edge of CONVERT begins the
conversion cycle. When conversion is completed DR returns
low. During the conversion cycle, HBE and LBE should be held
high. If HBE or LBE goes low during a conversion, the data
output buffers will be enabled and intermediate conversion re-
sults will be present on the data output pins. This may cause
bus conflicts if other devices in a system are trying to use the bus.
Reading the Data
The three-state data output buffers are enabled by HBE and
LBE. Access time of these buffers is typically 150 ns (250 maxi-
mum). The data outputs remain valid until 50 ns after the en-
able signal returns high, and are completely into the high
impedance state 100 ns later.
TIMING SPECIFICATIONS (All grades, T
Parameter
CONVERT Pulse Width
DR Delay from CONVERT t
Conversion Time
Data Access Time
Data Valid after HBE/LBE
Output Float Delay
MICROPROCESSOR INTERFACE CONSIDERATIONS—
GENERAL
When an analog-to-digital converter like the AD573 is inter-
faced to a microprocessor, several details of the interface must
be considered. First, a signal to start the converter must be gen-
erated; then an appropriate delay period must be allowed to pass
before valid conversion data may be read. In most applications,
the AD573 can interface to a microprocessor system with little
or no external logic.
The most popular control signal configuration consists of de-
coding the address assigned to the AD573, then gating this sig-
nal with the system’s WR signal to generate the CONVERT
High
CONVERT
LBE OR HBE
DB0–DB7
DB8–DB9
DR
OR
V
IH
+ V
2
IMPEDANCE
IL
Figure 9. Convert Timing
V
Figure 10. Read Timing
HIGH
IH
t
+ V
2
CS
t
DSC
IL
V
V
t
OH
Symbol Min Typ Max Units
t
t
t
t
t
DD
OL
CS
DSC
C
DD
HD
HL
V
OH
+ V
2
VALID
DATA
OL
t
C
500 –
–
10
0
50
–
t
HD
t
HL
1
20
150
–
100
A
= T
IMPEDANCE
MIN
–
1.5
30
250
–
200
HIGH
–T
MAX
ns
ns
ns
ns
s
s
)
–6–
pulse, and gating it with RD to enable the output buffers. The
use of a memory address and memory WR and RD signals de-
notes “memory-mapped” I/O interfacing, while the use of a
separate I/O address space denotes “isolated I/O” interfacing. In
8-bit bus systems, the 10-bit AD573 will occupy two locations
when data is to be read; therefore, two (usually consecutive) ad-
dresses must be decoded. One of the addresses can also be used
as the address which produces the CONVERT signal during
WR operations.
Figure 11 shows a generalized diagram of the control logic for
an AD573 interfaced to an 8-bit data bus, where two addresses
(ADC ADDR and ADC ADDR + 1) have been decoded. ADC
ADDR starts the converter when written to (the actual data be-
ing written to the converter does not matter) and contains the
high byte data during read operations. ADC ADDR + 1 per-
forms no function during write operations, but contains the low
byte data during read operations.
In systems where this read-write interface is used, at least 30
microseconds (the maximum conversion time) must be allowed
to pass between starting a conversion and reading the results.
This delay or “timeout” period can be implemented in a short
software routine such as a countdown loop, enough dummy in-
structions to consume 30 microseconds, or enough actual useful
instructions to consume the required time. In tightly-timed sys-
tems, the DR line may be read through an external three-state
buffer to determine precisely when a conversion is complete.
Higher speed systems may choose to use DR to signal an inter-
rupt to the processor at the end of a conversion.
Figure 11. General AD573 Interface to 8-Bit Microprocessor
Figure 12. Typical AD573 Interface Timing Diagram
REV. A