LT1765-2.5 Linear Technology, LT1765-2.5 Datasheet - Page 13

• Manufacturer Part Number: LT1765-2.5
• Description: Monolithic 3A/ 1.25MHz Step-Down Switching Regulator
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
Example: with V
Total power dissipation, P
Thermal resistance for the LT1765 16-lead TSSOP ex-
posed pad package is influenced by the presence of
internal or backside planes. With a full plane under the
package, thermal resistance will be about 45 C/W. With
no plane under the package, thermal resistance will in-
crease to about 110 C/W. For the exposed pad package
board performance. To calculate die temperature, use the
appropriate thermal resistance number and add in worst-
case ambient temperature:
When estimating ambient, remember the nearby catch
diode will also be dissipating power.
Notice that the catch diode’s forward voltage contributes
a significant loss in the overall system efficiency. A larger,
lower V
Typical thermal resistance of the board
ambient temperature of 25 C,
JC(PAD)
T
V
P
P
P
P
P
T
T
J
SW
Q
DIODE
F
DIODE
BOOST
J
J
= T
= Forward voltage of diode (assume 0.5V at 2A)
= T
= 25 + 45 (0.8) + 35 (0.5) = 79 C
F
10 0 001 0 01
A
0 26 0 43 0 69
A
= 10 C/W. Thermal resistance is dominated by
diode can improve efficiency by several percent.
+
.
0 13 2
+
.
.
JA
V V
0 5 10 5 2
5
JA
F
.
10
2
(P
(P
IN
.
10
2 50
TOT
TOT
IN
= 10V, V
10
2
U
/
5
.
)
) +
V
V
IN
OUT
W
.
TOT
U
B
17 10
OUT
0 1
(P
W
.
, is 0.69 + 0.1 + 0.01 = 0.8W.
DIODE
•
I
W
LOAD
0 5
= 5V and I
.
W
9
W
)
2 10 1 25 10
B
is 35 C/W. At an
OUT
= 2A:
.
U
•
6
DIE TEMPERATURE MEASUREMENT
If a true die temperature is required, a measurement of the
SYNC to GND pin resistance can be used. The SYNC pin
resistance across temperature must first be calibrated,
with no significant output load, in an oven. An initial value
of 40k with a temperature coefficient of 0.16%/ C is
typical. The same measurement can then be used in
operation to indicate the die temperature.
FREQUENCY COMPENSATION
Before starting on the theoretical analysis of frequency
response, the following should be remembered—the worse
the board layout, the more difficult the circuit will be to
stabilize. This is true of almost all high frequency analog
circuits, read the ‘LAYOUT CONSIDERATIONS’ section
first. Common layout errors that appear as stability prob-
lems are distant placement of input decoupling capacitor
and/or catch diode, and connecting the V
to a ground track carrying significant switch current. In
addition, the theoretical analysis considers only first order
ideal component behavior. For these reasons, it is impor-
tant that a final stability check is made with production
layout and components.
The LT1765 uses current mode control. This alleviates
many of the phase shift problems associated with the
inductor. The basic regulator loop is shown in Figure 7,
with both tantalum and ceramic capacitor equivalent cir-
cuits. The LT1765 can be considered as two g
error amplifier and the power stage.
LT1765/LT1765-1.8/LT1765-2.5/
LT1765
GND
CURRENT MODE
POWER STAGE
g
m
= 5mho
V
R
C
C
C
Figure 7. Model for Loop Response
C
500k
850 mho
C
g
AMPLIFIER
LT1765-3.3/LT1765-5
m
F
ERROR
=
–
+
V
1.2V
SW
FB
R1
R2
+
1765 F07
TANTALUM
ESR
C1
C
OUTPUT
compensation
m
blocks, the
sn1765 1765fas
CERAMIC
13
ESL
C1