MC14027B
Dual J−K Flip−Flop
Set (S) and Reset (R) inputs for each flip−flop. These devices may be
used in control, register, or toggle functions.
Features
•
•
•
•
•
•
•
•
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Temperature Derating:
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
to the range V
either V
*For additional information on our Pb−Free strategy and soldering details, please
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2005
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
Symbol
V
I
The MC14027B dual J−K flip−flop has independent J, K, Clock (C),
This device contains protection circuitry to guard against damage due to high
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
Low; Information is Transferred to the Output Only on the
Positive−Going Edge of the Clock Pulse
Schottky TTL Load Over the Rated Temperature Range
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge−Clocked Flip−Flop Design
Logic State is Retained Indefinitely with Clock Level Either High or
Capable of Driving Two Low−Power TTL Loads or One Low−Power
Pin−for−Pin Replacement for CD4027B
Pb−Free Packages are Available*
in
in
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
V
T
P
, V
, I
T
T
DD
stg
D
A
L
out
out
SS
or V
DC Supply Voltage Range
Input or Output Voltage Range
Input or Output Current
Power Dissipation, per Package
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
SS
DD
(DC or Transient)
(DC or Transient) per Pin
(Note 1)
(8−Second Soldering)
v (V
). Unused outputs must be left open.
in
Parameter
or V
(Voltages Referenced to V
out
) v V
DD
.
in
and V
−0.5 to V
−0.5 to +18.0
SS
−55 to +125
−65 to +150
out
)
Value
± 10
500
260
should be constrained
DD
+ 0.5
1
Unit
mW
mA
°C
°C
°C
V
V
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
A
WL, L
YY, Y
WW, W
G
CASE 751B
SOEIAJ−16
CASE 648
CASE 966
P SUFFIX
D SUFFIX
F SUFFIX
PDIP−16
SOIC−16
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Indicator
Publication Order Number:
16
1
16
16
1
1
DIAGRAMS
MARKING
MC14027BCP
AWLYYWWG
MC14027B
AWLYWW
MC14027B/D
14027BG
ALYWG