LTC1291 Linear Technology, LTC1291 Datasheet
LTC1291
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LTC1291 Summary of contents
Page 1
... A/D conversion. The input multiplexer can be configured for either single-ended or differential in- puts. An on-chip sample-and-hold is included on the “+” input. When the LTC1291 is idle, it can be powered down in applications where low power consumption is desired. An external reference is not required because the LTC1291 takes its reference from the power supply (V features are packaged in an 8-pin DIP ...
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... Digital Inputs........................................ –0.3V to 12V Digital Outputs .......................... –0. Power Dissipation............................................. 500mW Operating Temperature Range LTC1291BC, LTC1291CC, LTC1291DC ............................................ LTC1291BI, LTC1291CI, LTC1291DI ........................................ – LTC1291BM, LTC1291CM, LTC1291DM ................................... – 125 C Storage Temperature Range ................ – 150 C Lead Temperature (Soldering, 10 sec.)................ 300 ...
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... CS High CC = 0V, CS High = LTC1291BC, LTC1291CC, LTC1291DC LTC1291BI, LTC1291CI, LTC1291DI, LTC1291BM, LTC1291CM, LTC1291DM Note 7: Two on-chip diodes are tied to each analog input which will conduct for analog voltages one diode drop below GND or one diode drop above careful during testing at low V ...
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... LTC1291 W U TYPICAL PERFOR A Supply Current vs Supply Voltage 10 CLK = 1MHz T = 25° SUPPLY VOLTAGE (V) 1291 G01 Change in Linearity vs Supply Voltage 0.5 0.4 0.3 0.2 0.1 0 4.0 4.5 5.5 5.0 SUPPLY VOLTAGE (V) 1291 G04 Change in Linearity vs Temperature 0 CLK = 1MHz 0.4 0.3 0.2 0.1 0 – 125 –25 100 AMBIENT TEMPERATURE (°C) 1291 G07 * AS THE CLK FREQUENCY IS DECREASED FROM 1MHz, MINIMUM CLK FREQUENCY ( ERROR 0 ...
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... CTIO S # PIN FUNCTION DESCRIPTION 1 CS Chip Select Input A logic low on this input enables the LTC1291 CH0, CH1 Analog Inputs These inputs must be free of noise with respect to GND. 4 GND Analog Ground GND should be tied directly to an analog ground plane. 5 ...
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... LTC1291 W BLOCK I D AGRA REF INPUT 5 SHIFT D IN REGISTER 2 CH0 ANALOG 3 INPUT MUX CH1 4 GND TEST CIRCUITS Load Circuit for dDO 1. OUT 100pF On and Off Channel Leakage Current OFF A POLARITY 6 SAMPLE AND HOLD COMP 12-BIT ...
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... D OUT PPLICATI S I FOR ATIO The LTC1291 is a data acquisition component which contains the following functional blocks: 1. 12-bit successive approximation capacitive A/D converter 2. Analog multiplexer (MUX) 3. Sample-and-hold (S/H) 4. Synchronous, half duplex serial interface 5. Control and timing logic DIGITAL CONSIDERATIONS Serial Interface ...
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... DATA ( Data transfer is initiated by a falling chip IN OUT select (CS) signal. After CS falls the LTC1291 looks for a start bit. After the start bit is received a 4-bit input word is shifted into the D input which configures the LTC1291 IN and starts the conversion. After one null bit, the result of ...
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... MSB-First/LSB-First (MSBF) PS The output data of the LTC1291 is programmed for MSB- POWER first or LSB-first sequence using the MSBF bit. When the SHUTDOWN MSBF bit is a logical one, data will appear on the D 1291 F02 in MSB-first format. Logical zeroes will be filled in indefi- nitely following the last data bit to accommodate longer word lengths required by some microprocessors ...
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... Table 1 MPU without a dedicated serial port is used, then three of the MPU’s parallel port lines can be programmed to form the serial link to the LTC1291. Included here are one serial interface example and one example showing a parallel port pro- grammed to form the serial interface. ...
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... WORD BYTE 1 MPU ? ? ? ? ? ? ? RECEIVED WORD BYTE 1 Hardware and Software Interface to Motorola MC68HC11 D OUT FROM LTC1291 STORED IN MC68HC11 RAM MSB 0 # LSB #63 MC68HC11 CODE In this example the D word configures the input MUX for IN a single-ended input to be applied to CH0. The conversion result is output MSB-first ...
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... D lines together. The 8051 first sends the start bit OUT and MUX Address to the LTC1291 over the line connected to P1.2. Then P1.2 is reconfigured as an input and the 8051 reads back the 12-bit A/D result over the same data line. Timing Diagram for Interface to Intel 8051 ...
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... CLR CLR RLC MOV RLC SETB CLR MOV RLC SETB CLR MOV SETB RRC RRC RRC RRC MOV AJMP (Figure 3). The CS signals decide which LTC1291 is being addressed by MPU LTC1291 LTC1291 2 CHANNELS 2 CHANNELS 2 CHANNELS LTC1291 OPERAND COMMENTS P1.3 CLK GOES LOW ...
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... S I FOR ATIO ANALOG CONSIDERATIONS Grounding The LTC1291 should be used with an analog ground plane and single point grounding techniques. Do not use wire wrapping techniques to breadboard and evaluate the device. To achieve the optimum performance use a PC board. The ground pin (Pin 4) should be tied directly to the ground plane with minimum lead length ...
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... R P2 GND Figure 7. Parasitic Resistance in the V Source Resistance The analog inputs of the LTC1291 look like a 100pF capacitor ( series with a 500 resistor (R IN gets switched between “+” and “–” inputs once during each conversion cycle. Large external source resistors “ ...
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... INPUT MUST SETTLE DURING THIS TIME HI-Z 1ST BIT TEST “–” INPUT MUST Figure 9. “+” and “–” Input Settling Windows Figure 11. Poor Op Amp Settling Can Cause A/D Errors (Note Horizontal Scale) HOLD PS t SMPL B11 SETTLE DURING THIS TIME LTC1291 F09 HORIZONTAL: 20 s/DIV ...
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... The LTC1291 provides a built-in sample-and-hold (S/H) function on the +IN input for signals acquired in the single- ended mode (–IN pin grounded). The sample-and-hold W U allows the LTC1291 to convert rapidly varying signals (see typical performance characteristics curve of S/H Acquisition Time vs Source Resistance). The input voltage is sampled (e.g the F ...
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... A/D and possibly damage the device. For example this condition would occur if a signal is applied to the analog inputs before power is applied to the LTC1291. It can also happen if the input source is operating from supplies of larger value than the LTC1291 supply. These conditions should be prevented either with proper supply sequencing or by use of external circuitry to clamp or current limit the input source ...
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... Figure 16. “Quick Look” Circuit for the LTC1291 NULL MSB LSB FILLS WITH (B11) (B0) ZEROES BIT VERTICAL: 5V/DIV HORIZONTAL: 5 s/DIV Figure 17. Scope Trace of the LTC1291 "Quick Look" Circuit Showing Output 101010101010 (AAA LTC1291 outputs the data. OUT pin can be viewed on a OUT 5V 0 ...
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... LTC1291 PACKAGE DESCRIPTIO 0.290 – 0.320 (7.37 – 8.13) 0.008 – 0.018 0° – 15° (0.203 – 0.460) 0.014 – 0.026 0.385 ± 0.025 (0.360 – 0.660) (9.779 ± 0.635) 0.038 – 0.068 (0.965 – 1.727) 0.300 – 0.320 (7.620 – 8.128) 0.065 (1 ...