LTC1403 Linear Technology, LTC1403 Datasheet
LTC1403
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LTC1403 Summary of contents
Page 1
... MS package. A Sleep shutdown feature lowers power consumption The combination of speed, low power and tiny package makes the LTC1403/LTC1403A suitable for high speed, portable applications. The 80dB common mode rejection allows users to elimi- nate ground loops and common mode noise by measuring signals differentially from the source ...
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... Digital Input Voltage ................... – 0. Digital Output Voltage .................. – 0. Power Dissipation .............................................. 100mW Operation Temperature Range LTC1403C/LTC1403AC ............................ LTC1403I/LTC1403AI ......................... – Storage Temperature Range ................. – 150 C Lead Temperature (Soldering, 10 sec).................. 300 VERTER CHARACTERISTICS temperature range, otherwise specifications are at T ...
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... A DD OUT V = 2.7V 160 A DD OUT V = 2.7V 1.6mA DD OUT OUT 0V OUT OUT DD LTC1403/LTC1403A LTC1403 LTC1403A MIN TYP MAX MIN TYP MAX 70.5 73.5 68 70.5 70 73.5 72 76.3 72 76.3 –87 –90 –83 –76 –86 –78 –87 –90 –83 –86 –82 –82 ...
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... Note 16: Maximum clock period guarantees analog performance during conversion. Output data can be read without an arbitrarily long clock. Note 17 must be within this range. Note 18: The LTC1403A is measured and specified with 14-bit Resolution (1LSB = 152 V) and the LTC1403 is measured and specified with 12-bit Resolution (1LSB = 610 V). MIN TYP MAX 2.7 3 ...
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... FREQUENCY (Hz) Differential Linearity vs Output Code 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 4096 8192 12288 OUTPUT CODE LTC1403/LTC1403A (LTC1403A SFDR vs Input Frequency 104 100 0 FREQUENCY (MHz) 1403A G02 1.3MHz Sine Wave 4096 Point FFT Plot 0 2 ...
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... Differential and Integral Linearity vs Conversion Rate 5 18 CLOCKS PER CONVERSION –1 –2 –3 –4 –5 2.0 2.2 2.4 2.6 2.8 CONVERSION RATE (Msps (LTC1403 and LTC1403A 2.5V Power Bandwidth P –6 –12 –18 –24 –30 –36 1M 10M 100M 1G FREQUENCY (Hz) 1403A G07 Reference Voltage vs Load Current 2 ...
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... Four or more pulses with SCK in fixed high or fixed low state start Sleep mode & H 14-BIT ADC – 14 REF 2.5V REFERENCE EXPOSED PAD LTC1403/LTC1403A – analog inputs at the start of the previous IN THREE- STATE SDO SERIAL 8 OUTPUT PORT CONV 10 TIMING LOGIC 9 SCK 1403A BD 1403af ...
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... SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D11 D10 14-BIT DATA WORD t CONV t THROUGHPUT LTC1403A Timing Diagram HOLD t 10 SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION D13 D12 ...
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... During conversion, the analog inputs draw only a small leakage current. If the source impedance of the driving circuit is low, then the LTC1403/ LTC1403A inputs can be driven directly. As source imped- ance increases, so will acquisition time. For minimum acqui- sition time with high source impedance, a buffer amplifier must be used ...
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... W U 1403A F01 INPUT RANGE The analog inputs of the LTC1403/LTC1403A may be driven fully differentially with a single supply. Each input may swing range, the noninverting input of each channel is always up to 2.5V more positive than the inverting input of each channel. The 0V to 2.5V range is also ideally suited for single-ended input use with single supply applications ...
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... Figure 4 shows the ideal input/output characteristics for the LTC1403/LTC1403A. The code transitions occur mid- way between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, FS – 1.5LSB). The output code is natural binary with 1LSB = 2.5V/16384 = 153 V for the LTC1403A and 1LSB = 2.5V/4096 = 610 V for the LTC1403. The LTC1403A has 1LSB RMS of random white noise ...
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... LTC1403/LTC1403A. The SCK and CONV inputs con- trol the power-down modes (see Timing Diagrams). Two rising edges at CONV, without any intervening rising edges at SCK, put the LTC1403/LTC1403A. in Nap mode and the power drain drops from 14mW to 6mW. The internal reference remains powered in Nap mode. One or ...
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... A simple approach to generate CONV is to create a pulse that is one SCK wide to drive the LTC1403/LTC1403A and then buffer this signal with the appropriate number of inverters to ensure the correct delay driving the frame ...
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... The ADC’s serial data can be collected in two alternating 1kB segments, in real time, at the full 2.8Msps conversion rate of the LTC1403/ LTC1403A. The DSP assembly code sets frame sync mode at the BFSR pin to accept an external positive going pulse and the serial clock at the BCLKR pin to accept an external positive edge clock ...
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... TC = (@ar2 == #02000h) ; output buffer is 2k starting at 1800h if (TC) goto start ; restart if out buffer is at 1fffh goto bufull W U ;Set address of executable ;Set address of incoming 1403 data ;Set address of BSP buffer for clearing ;Set address of result for clearing ;.text marks start of code LTC1403/LTC1403A 1403af 15 ...
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... The data format is 16-bits, burst mode, with autobuffering * enabled. * ***************************************************************************************************** *LTC1403 timing from LCC28 socket board with 10MHz crystal. *10MHz, divided from 40MHz, forced to CLKIN by 1403 board. *Horizontal scale is 25ns/chr or 100ns period at BCLKR *Timing measured at DSP pins. Jxx pin labels for jumper cable. ...
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... The vectors in this table can be configured for processing external and ; internal software interrupts. The DSKplus debugger uses four interrupt ; vectors. These are RESET, TRAP2, INT2, and HPIINT NOT MODIFY THESE FOUR VECTORS IF YOU PLAN TO USE THE DEBUGGER * ; LTC1403/LTC1403A * * DLB bit FO bit MCM bit 10 ...
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... LTC1403/LTC1403A U U APPLICATIO S I FOR ATIO ; All other vector locations are free to use. When programming always be sure ; the HPIINT bit is unmasked (IMR=200h) to allow the communications kernel and ; host PC interact. INT2 should normally be masked (IMR(bit that the ; DSP will not interrupt itself during a HINT. HINT is tied to INT2 externally. ...
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... DETAIL “A” 0.254 0 – 6 TYP 0.53 0.152 (.021 .006) DETAIL “A” SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP LTC1403/LTC1403A BOTTOM VIEW OF EXPOSED PAD OPTION 2.06 0.102 (.081 .004) 1 1.83 0.102 (.072 .004) 10 0.497 0.076 (.0196 .003 REF 3 ...
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... LTC1403/LTC1403A RELATED PARTS PART NUMBER DESCRIPTION ADCs LTC1608 16-Bit, 500ksps Parallel ADC LTC1604 16-Bit, 333ksps Parallel ADC LTC1609 16-Bit, 250ksps Serial ADC LTC1411 14-Bit, 2.5Msps Parallel ADC LCT1414 14-Bit, 2.2Msps Parallel ADC LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package ...