LTC1550 Linear Technology, LTC1550 Datasheet - Page 5

• Manufacturer Part Number: LTC1550
• Description: Low Noise/ Switched Capacitor Regulated Voltage Inverters
• Manufacturer: Linear Technology

SHDN: Shutdown (TTL Compatible). This pin is active low
(SHDN) for the LTC1550 and active high (SHDN) for the
LTC1551. When this pin is at V
LTC1550 operates normally. When SHDN is pulled low
(high for LTC1551), the LTC1550 enters shutdown mode.
In shutdown, the charge pump stops, the output collapses
to 0V, and the quiescent current drops typically to 0.2 A.
V
4.5V and 6.5V for the fixed voltage LTC1550CS8-4.1/
LTC1551CS8-4.1. The adjustable voltage LTC1550CGN/
LTC1550IGN operates with a VCC range of 2.7V to 6.5V.
Output voltage and output load current conditions depend
on the VCC supply voltage. Consult the Electrical Charac-
teristics table and Typical Performance Characteristics for
guaranteed test points. The difference between the input
voltage and output should never be set to exceed 14V or
damage to the chip may occur. V
PGND (GND for 8-pin packages) with at least a 0.1 F
capacitor placed in close proximity to the chip. A 4.7 F or
larger bypass capacitor is recommended to minimize
noise and ripple at the output.
C1
C1
V
to ground with a 4.7 F or larger capacitor to ensure
TYPICAL PERFORMANCE CHARACTERISTICS
PIN
CC
OUT
+
+
U
: Power Supply. V
: C1 Positive Input. Connect a 0.1 F capacitor between
and C1
0.01
: Negative Voltage Output. This pin must be bypassed
0.1
10
1
FUNCTIONS
Spot Noise
(See Figure 2, C
1
U
–
.
FREQUENCY (kHz)
CC
U
OUT
10
requires an input voltage between
= 10 F)
W
V
I
C
C
C
L
CC
IN
OUT
L
CC
= 5mA
= 0.1 F
LTC1550/51 • G12
= 4.7 F
= 5V
= 10 F
(GND for LTC1551), the
CC
U
must be bypassed to
100
–10
90
80
70
60
50
40
30
20
10
0
100k
Output Spectrum
(See Figure 2, C
V
I
C
C
C
L
CC
IN
OUT
L
= 5mA
= 0.1 F
4.7 F
= 5V
= 22 F
FREQUENCY (Hz)
regulator loop stability. At least 10 F is recommended to
provide specified output ripple. An additional 0.1 F low
ESR capacitor is recommended to minimize high fre-
quency spikes at the output.
C1
C1
GND: Ground. Connect to a low impedance ground. A
ground plane will help minimize regulation errors.
CP
0.1 F storage capacitor to ground.
SENSE: Connect to V
regulator uses this pin to sense the output voltage. For
optimum regulation, SENSE should be connected close to
the output load.
SSOP PACKAGE ONLY
PGND: Power Ground. Connect to a low impedance ground.
PGND should be connected to the same potential as
AGND.
AGND: Analog Ground. Connect to a low impedance
ground. AGND should be connected to a ground plane to
minimize regulation errors.
1M
OUT
OUT
–
+
: C1 Negative Input. Connect a 0.1 F capacitor from
to C1
= 22 F)
: Negative Charge Pump Output. This pin requires a
–
.
LT1550/51 • G13
10M
OUT
0.01
0.1
10
. The LTC1550/LTC1551 internal
LTC1550/LTC1551
1
Spot Noise
(See Figure 2, C
1
FREQUENCY (kHz)
OUT
10
= 22 F)
V
I
C
C
C
L
CC
IN
OUT
L
= 5mA
= 0.1 F
= 4.7 F
LTC1550/51 • G14
= 5V
= 22 F
5
100