LTC1743 Linear Technology, LTC1743 Datasheet - Page 12

• Manufacturer Part Number: LTC1743
• Description: 12-Bit 50Msps ADC
• Manufacturer: Linear Technology

APPLICATIO S I FOR ATIO
LTC1743
Aperture Delay Time
The time from when a rising ENC equals the ENC voltage
to the instant that the input signal is held by the sample and
hold circuit.
Aperture Delay Jitter
The variation in the aperture delay time from conversion to
conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
to the jitter alone will be:
CONVERTER OPERATION
As shown in Figure 1, the LTC1743 is a CMOS pipelined
multistep converter. The converter has four pipelined ADC
stages; a sampled analog input will result in a digitized
value five cycles later, see the Timing Diagram section.
The analog input is differential for improved common
12
SENSE
4.7 F
SNR
A
A
V
IN
IN
CM
+
–
JITTER
INPUT
REFERENCE
S/H
SELECT
RANGE
2.5V
= – 20log (2 ) • F
REF
BUF
U
U
FIRST STAGE
ADC STAGE
PIPELINED
5-BIT
IN
• T
DIFF
AMP
REF
W
JITTER
0.1 F
REFLB
1 F
REFERENCES TO ADC
Figure 1. Functional Block Diagram
REFHA
INTERNAL
4.7 F
U
SECOND STAGE
ADC STAGE
PIPELINED
4-BIT
REFLA
1 F
0.1 F
REFHB
CLOCK SIGNALS
mode noise immunity and to maximize the input range.
Additionally, the differential input drive will reduce even
order harmonics of the sample-and-hold circuit. The en-
code input is also differential for improved common mode
noise immunity.
The LTC1743 has two phases of operation, determined by
the state of the differential ENC/ENC input pins. For brev-
ity, the text will refer to ENC greater than ENC as ENC high
and ENC less than ENC as ENC low.
Each pipelined stage shown in Figure 1 contains an ADC,
a reconstruction DAC and an interstage residue amplifier.
In operation, the ADC quantizes the input to the stage and
the quantized value is subtracted from the input by the
DAC to produce a residue. The residue is amplified and
output by the residue amplifier. Successive stages operate
out of phase so that when the odd stages are outputting
their residue, the even stages are acquiring that residue
and visa versa.
DIFFERENTIAL
LOW JITTER
INTERNAL
DRIVER
CLOCK
INPUT
ENC
ENC
THIRD STAGE
ADC STAGE
PIPELINED
4-BIT
MSBINV
CONTROL
LOGIC
SHIFT REGISTER AND CORRECTION
OE
FOURTH STAGE
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FLASH
2-BIT
ADC
DRIVERS
OUTPUT
OGND
OV
0.5V TO
5V
OF
D11
D0
CLKOUT
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•
•
1743f
1743 F01
DD