LTC2053 Linear Technology, LTC2053 Datasheet - Page 10

• Manufacturer Part Number: LTC2053
• Description: Precision/ Rail-to-Rail Input and Output/ Zero-Drift Instrumentation Amplifier with Resistor-Programmable Gain
• Manufacturer: Linear Technology

LTC2053
APPLICATIO S I FOR ATIO
Settling Time
The sampling rate is 3kHz and the input sampling period
during which C
V
input sampling period, C
= C
of accuracy at the op amp noninverting input after N clock
cycles or 333 s(N). The settling time at the OUT pin is also
affected by the settling of the internal op amp. Since the
gain bandwidth of the internal op amp is typically 200kHz,
the settling time is dominated by the switched capacitor
front end for gains below 100 (see Typical Performance
Characteristics).
Input Current
Whenever the differential input V
charged up to the new input voltage via C
an input charging current during each input sampling
period. Eventually, C
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on C
voltage. For example, the parasitic bottom plate capacitor
on C
the voltage on the –IN pin every cycle. The resulting input
10
IN
H
is approximately 150 s. First assume that on each
S
(= 1000pF), a change in the input will settle to N bits
must be charged from the voltage on the REF pin to
S
is charged to the input differential voltage
U
H
and C
S
S
is charged fully to V
every cycle even if V
U
S
will reach V
V
V
SINGLE SUPPLY, UNITY GAIN
–IN
+IN
IN
V
changes, C
–
W
+
D
3
2
0V < V
0V < V
0V < V
V
OUT
+
–
5V
S
. This results in
= V
8
4
IN
+IN
–IN
D
< 3.7V
D
< 5V
< 5V
and, ideally,
IN
5
H
IN
. Since C
U
must be
6
is a DC
7
V
OUT
Figure 1
S
–5V < V
–5V < V
–5V < V
V
V
V
OUT
+IN
–IN
charging current decays exponentially during each input
sampling period with a time constant equal to R
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors
due to source resistance or the source resistance mis-
match between –IN and +IN. With R
DC errors occur due to this input current.
In the Typical Performance Characteristics section of this
data sheet, there are curves showing the additional error
from non-zero source resistance in the inputs. If there are
no large capacitors across the inputs, the amplifier is less
sensitive to source resistance and source resistance mis-
match. When large capacitors are placed across the in-
puts, the input charging currents described above result in
larger DC errors, especially with source resistor mis-
matches.
Power Supply Bypassing
The LTC2053 uses a sampled data technique and therefore
contains some clocked digital circuitry. It is therefore
sensistive to supply bypassing. For single or dual supply
operation, a 0.1 F ceramic capacitor must be connected
between Pin 8 (V
possible.
= 1 +
V
+
–
–IN
+IN
D
D
DUAL SUPPLY
+ V
3
2
< 5V AND
< 5V AND
REF
R2
R1
+
–
–5V
5V
< 3.7V
8
4
V
D
V
+ V
REF
5
REF
V
V
+IN
–IN
6 R2
R1
7
– V
– V
+
) and Pin 4 (V
REF
REF
2053 F01
< 5.5V
< 5.5V
V
OUT
–
) with leads as short as
S
less than 10k, no
S
C
S
. If the
2053fa