LTC2223 Linear Technology, LTC2223 Datasheet

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LTC2223

Manufacturer Part Number
LTC2223
Description
(LTC2222 / LTC2223) 105Msps/80Msps ADCs
Manufacturer
Linear Technology
Datasheet

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FEATURES
APPLICATIO S
TYPICAL APPLICATIO
ANALOG
INPUT
REFH
REFL
Sample Rate: 105Msps/80Msps
68dB SNR up to 140MHz Input
80dB SFDR up to 170MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 475mW/366mW
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
135Msps: LTC2224 (12-Bit), LTC2234 (10-Bit)
105Msps: LTC2222 (12-Bit), LTC2232 (10-Bit)
80Msps: LTC2223 (12-Bit), LTC2233 (10-Bit)
48-Pin QFN Package
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
+
CLOCK/DUTY
REFERENCE
INPUT
CONTROL
FLEXIBLE
ENCODE
S/H
CYCLE
INPUT
U
PIPELINED
ADC CORE
12-BIT
U
3.3V
V
DD
CORRECTION
LOGIC
DRIVERS
OUTPUT
DESCRIPTIO
The LTC
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2222/
LTC2223 are perfect for demanding communications
applications with AC performance that includes 68dB SNR
and 80dB spurious free dynamic range for signals
up to 170MHz. Ultralow jitter of 0.15ps
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.3LSB INL (typ), ±0.2LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.5LSB
A separate output power supply allows the outputs to drive
0.5V to 3.6V logic.
The ENC
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
All other trademarks are the property of their respective owners.
22201 TA01
, LTC and LT are registered trademarks of Linear Technology Corporation.
®
+
2222 and LTC2223 are 105Msps/80Msps, sam-
D11
0V
0.5V TO 3.6V
0GND
D0
and ENC
DD
U
LTC2222/LTC2223
inputs may be driven differentially or
RMS
100
12-Bit,105Msps/
95
90
85
80
75
70
65
60
.
0
80Msps ADCs
SFDR vs Input Frequency
100
INPUT FREQUENCY (MHz)
200
4th OR HIGHER
300
2nd or 3rd
400
RMS
500
allows
22223 TA01b
22223fa
1
600

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