LTC2240-10 Linear Technology, LTC2240-10 Datasheet
LTC2240-10
Related parts for LTC2240-10
LTC2240-10 Summary of contents
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... CONTROL ENCODE INPUT DESCRIPTION The LTC verter designed for digitizing high frequency, wide dynamic range signals. The LTC2240-10 is perfect for demanding communications applications with AC performance that includes 60.6dB SNR and 80dB SFDR. Ultralow jitter of 95fs RMS performance. DC specs include ±0.3LSB INL (typ), ±0.1LSB DNL (typ) and no missing codes over temperature ...
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... LTC2240-10 ABSOLUTE MAXIMUM RATINGS Supply Voltage (V ) ...............................................2.8V DD Digital Output Ground Voltage (OGND) ........ –0. Analog Input Voltage (Note 3) .......–0. www.datasheet4u.com Digital Input Voltage ......................–0. Digital Output Voltage ................ –0.3V to (OV PIN CONFIGURATION ORDER INFORMATION LEAD FREE FINISH TAPE AND REEL ...
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... IN CONDITIONS 10MHz Input 70MHz Input 140MHz Input 240MHz Input 10MHz Input 70MHz Input 140MHz Input 240MHz Input 10MHz Input 70MHz Input 140MHz Input 240MHz Input LTC2240-10 MIN TYP –0.8 ±0.3 l –0.6 ±0.1 l –15 ±5 l –3.8 ± ...
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... LTC2240-10 DYNAMIC ACCURACY otherwise specifi cations are 25° SYMBOL PARAMETER S/(N+D) Signal-to-Noise Plus www.datasheet4u.com Distortion Ratio (Note 12) IMD Intermodulation Distortion INTERNAL REFERENCE CHARACTERISTICS PARAMETER V Output Voltage CM V Output Tempco CM V Line Regulation CM V Output Resistance CM DIGITAL INPUTS AND DIGITAL OUTPUTS full operating temperature range, otherwise specifi ...
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... Duty Cycle Stabilizer Off Duty Cycle Stabilizer On Duty Cycle Stabilizer Off Duty Cycle Stabilizer On (Note 7) (Note 7) (Note 7) (t – (Note (Note 7) (Note 7) LTC2240-10 l denotes the specifi cations which apply over the MIN TYP MAX l 247 350 454 l 1.125 1.250 1.375 ...
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... LTC2240-10 TIMING CHARACTERISTICS range, otherwise specifi cations are at T SYMBOL PARAMETER DATA to CLKOUT Skew www.datasheet4u.com Pipeline Latency Full Rate CMOS Demuxed Interleaved Demuxed Simultaneous ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime ...
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... RANGE 100 200 300 400 500 600 700 1000 INPUT FREQUENCY (MHz) 224010 G10 LTC2240- 25°C unless otherwise noted, Note 4) A 8192 Point FFT –1dB, 2V Range, LVDS Mode 0 –10 –20 –30 –40 –50 –60 –70 –80 – ...
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... LTC2240-10 TYPICAL PERFORMANCE CHARACTERISTICS SFDR and SNR vs Sample Rate, 2V Range 30MHz, –1dB, IN LVDS Mode www.datasheet4u.com 90 85 SFDR SNR 100 120 140 160 180 SAMPLE RATE (Msps Sample Rate, 5MHz Sine VDD Wave Input, –1dB 190 ...
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... Output and Input Common Mode Bias. CM Bypass to ground with 2.2μF ceramic chip capacitor. GND (Exposed Pad) (Pin 65): ADC Power Ground. The exposed pad on the bottom of the package needs to be soldered to ground. LTC2240-10 selects demux CMOS DD selects offset DD selects 2’s complement DD selects 2’ ...
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... LTC2240-10 PIN FUNCTIONS (LVDS Mode) + AIN (Pins 1, 2): Positive Differential Analog Input. – AIN (Pins 3, 4): Negative Differential Analog Input. www.datasheet4u.com REFHA (Pins 5, 6): ADC High Reference. Bypass to Pins 7, 8 with 0.1μF ceramic chip capacitor, to Pins 11, 12 with a 2.2μF ceramic capacitor and to ground with 1μF ceramic capacitor ...
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... CLOCK DRIVER REFLB REFHA REFLA REFHB 2.2μF + – ENC ENC 0.1μF 0.1μF 1μF 1μF Figure 1. Functional Block Diagram LTC2240-10 FOURTH PIPELINED FIFTH PIPELINED ADC STAGE ADC STAGE SHIFT REGISTER AND CORRECTION CONTROL OUTPUT LOGIC DRIVERS 224010 F01 OGND LVDS SHDN M0DE ...
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... LTC2240-10 TIMING DIAGRAMS www.datasheet4u.com ANALOG INPUT – ENC + ENC D0-D9, OF – CLKOUT + CLKOUT ANALOG INPUT – ENC + ENC DA0-DA9, OFA CLKOUTB CLKOUTA DB0-DB9, OFB 12 LVDS Output Mode Timing All Outputs Are Differential and Have LVDS Levels – ...
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... All Outputs Are Single-Ended and Have CMOS Levels – – LTC2240- – – – 2 224010 TD03 – – – – 1 224010 TD04 224010fb 13 ...
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... AC input. The signal to noise ratio due to the jitter alone will be: SNR CONVERTER OPERATION As shown in Figure 1, the LTC2240- CMOS pipelined multi-step converter. The converter has fi ve pipelined ADC stages; a sampled analog input will result in a digitized value fi ve cycles later (see the Timing Diagram section). For optimal performance the analog inputs should be driven differentially ...
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... SAMPLE/HOLD OPERATION AND INPUT DRIVE Sample/Hold Operation Figure 2 shows an equivalent circuit for the LTC2240-10 CMOS differential sample-and-hold. The analog inputs are connected to the sampling capacitors (C NMOS transistors. The capacitors shown attached to ...
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... Poor matching will result in higher even order harmonics, especially the second. Input Drive Circuits Figure 3 shows the LTC2240-10 being driven transformer with a center tapped secondary. The secondary center tap is DC biased with V CM signal at its optimum DC level ...
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... ADC bandwidth. Reference Operation Figure 9 shows the LTC2240-10 reference circuitry consist- ing of a 1.25V bandgap reference, a difference amplifi er and switching and control circuit. The internal voltage reference can be confi gured for two pin selectable input ranges of 2V (± ...
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... Characteristics section. BUFFER Driving the Encode Inputs INTERNAL ADC HIGH REFERENCE The noise performance of the LTC2240-10 can depend on the encode signal quality as much as on the analog input. The ENC DIFF AMP differentially, primarily for noise immunity from com- mon mode noise sources. Each input is biased through a 4 ...
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... PLL to lock onto the input clock. To use the clock duty cycle stabilizer, the MODE pin should be connected to 1/3V The lower limit of the LTC2240-10 sample rate is determined by droop of the sample-and-hold circuits. The pipelined architecture of this ADC relies on storing analog signals on small valued capacitors. Junction leakage will discharge the capacitors. The specifi ...
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... As with all high speed/high resolution converters, the 10 0000 0000 digital output loading can affect the performance. The digital outputs of the LTC2240-10 should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. The output should be buffered with a device such as an 74VCX245 CMOS latch ...
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... LOGIC LATCH OE Figure 13a. Digital Output Buffer in CMOS Mode Data Format The LTC2240-10 parallel digital output can be selected for offset binary or 2’s complement format. The format is selected with the MODE pin. Connecting MODE to GND or 1/3V selects offset binary output format. Connecting ...
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... HEAT TRANSFER Most of the heat generated by the LTC2240-10 is trans- ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. For good electrical and thermal performance, the exposed ...
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... If your clock is also used to drive digital devices such as an FPGA, you should locate the oscillator, and any clock LTC2240-10 fan-out devices close to the ADC, and give the routing to the ADC precedence. The clock signals to the FPGA ...
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... LTC2240-10 APPLICATIONS INFORMATION www.datasheet4u.com GND 16 GND 61 GND 64 GND ...
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... APPLICATIONS INFORMATION Silkscreen Top www.datasheet4u.com Layer 1 Component Side LTC2240-10 Layer 2 GND Plane Layer 3 Power/Ground Plane 25 224010fb ...
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... LTC2240-10 APPLICATIONS INFORMATION Layer 4 Power/Ground Planes www.datasheet4u.com Layer 5 Power/Ground Planes 26 Layer Back Solder Side Silk Screen Back, Solder Side 224010fb ...
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... PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 0.75 ± 0.05 7.15 ± 0.10 (4-SIDES) 0.200 REF 0.00 – 0.05 LTC2240-10 NOTE: 1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 2. ALL DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT 4 ...
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... LTC2240-10 RELATED PARTS PART NUMBER DESCRIPTION LTC1748 14-Bit, 80Msps, 5V ADC www.datasheet4u.com LTC1750 14-Bit, 80Msps, 5V Wideband ADC ® LT 1993-2 High Speed Differential Op Amp LT1994 Low Noise, Low Distortion Fully Differential Input/Output Amplifi er/Driver LTC2202 16-Bit, 10Msps, 3.3V ADC, Lowest Noise LTC2208 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs LTC2220 12-Bit, 170Msps, 3 ...